| # -*- mode:python -*- |
| |
| # Copyright (c) 2006 The Regents of The University of Michigan |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Steve Reinhardt |
| |
| Import('*') |
| |
| DebugFlag('Activity') |
| DebugFlag('Commit') |
| DebugFlag('Context') |
| DebugFlag('Decode') |
| DebugFlag('DynInst') |
| DebugFlag('ExecEnable', |
| 'Filter: Enable exec tracing (no tracing without this)') |
| DebugFlag('ExecCPSeq', 'Format: Instruction sequence number') |
| DebugFlag('ExecEffAddr', 'Format: Include effective address') |
| DebugFlag('ExecFaulting', 'Trace faulting instructions') |
| DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number') |
| DebugFlag('ExecOpClass', 'Format: Include operand class') |
| DebugFlag('ExecRegDelta') |
| DebugFlag('ExecResult', 'Format: Include results from execution') |
| DebugFlag('ExecSymbol', 'Format: Try to include symbol names') |
| DebugFlag('ExecThread', 'Format: Include thread ID in trace') |
| DebugFlag('ExecTicks', 'Format: Include tick count') |
| DebugFlag('ExecMicro', 'Filter: Include microops') |
| DebugFlag('ExecMacro', 'Filter: Include macroops') |
| DebugFlag('ExecUser', 'Filter: Trace user mode instructions') |
| DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') |
| DebugFlag('ExecAsid', 'Format: Include ASID in trace') |
| DebugFlag('ExecFlags', 'Format: Include instruction flags in trace') |
| DebugFlag('Fetch') |
| DebugFlag('IntrControl') |
| DebugFlag('O3PipeView') |
| DebugFlag('PCEvent') |
| DebugFlag('Quiesce') |
| DebugFlag('Mwait') |
| |
| CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr', |
| 'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta', |
| 'ExecResult', 'ExecSymbol', 'ExecThread', |
| 'ExecTicks', 'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel', |
| 'ExecAsid', 'ExecFlags' ]) |
| CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', |
| 'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro', |
| 'ExecFaulting', 'ExecUser', 'ExecKernel' ]) |
| CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', |
| 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting', |
| 'ExecUser', 'ExecKernel' ]) |
| |
| Source('pc_event.cc') |
| |
| if env['TARGET_ISA'] == 'null': |
| SimObject('IntrControl.py') |
| Source('intr_control_noisa.cc') |
| Return() |
| |
| # Only build the protocol buffer instructions tracer if we have protobuf support |
| if env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86': |
| SimObject('InstPBTrace.py') |
| Source('inst_pb_trace.cc') |
| |
| SimObject('CheckerCPU.py') |
| |
| SimObject('BaseCPU.py') |
| SimObject('CPUTracers.py') |
| SimObject('FuncUnit.py') |
| SimObject('IntrControl.py') |
| SimObject('TimingExpr.py') |
| |
| Source('activity.cc') |
| Source('base.cc') |
| Source('cpuevent.cc') |
| Source('exetrace.cc') |
| Source('exec_context.cc') |
| Source('func_unit.cc') |
| Source('inteltrace.cc') |
| Source('intr_control.cc') |
| Source('nativetrace.cc') |
| Source('profile.cc') |
| Source('quiesce_event.cc') |
| Source('reg_class.cc') |
| Source('static_inst.cc') |
| Source('simple_thread.cc') |
| Source('thread_context.cc') |
| Source('thread_state.cc') |
| Source('timing_expr.cc') |
| |
| SimObject('DummyChecker.py') |
| SimObject('StaticInstFlags.py') |
| Source('checker/cpu.cc') |
| Source('dummy_checker.cc') |
| DebugFlag('Checker') |
