| // Copyright (c) 2015 ARM Limited | |
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| #ifndef EXT_SST_GEM5_HH | |
| #define EXT_SST_GEM5_HH | |
| #include <string> | |
| #include <vector> | |
| #include <core/sst_config.h> | |
| #include <core/component.h> | |
| #include <sim/simulate.hh> | |
| #include "ExtMaster.hh" | |
| #include "ExtSlave.hh" | |
| namespace SST { | |
| namespace gem5 { | |
| class gem5Component : public SST::Component, | |
| public ExternalSlave::Handler, | |
| public ExternalMaster::Handler { | |
| private: | |
| Output dbg; | |
| Output info; | |
| uint64_t sim_cycles; | |
| uint64_t clocks_processed; | |
| std::vector<ExtMaster*> masters; | |
| std::vector<ExtSlave*> slaves; | |
| void splitCommandArgs(std::string &cmd, std::vector<char*> &args); | |
| void initPython(int argc, char *argv[]); | |
| public: | |
| gem5Component(ComponentId_t id, Params ¶ms); | |
| ~gem5Component(); | |
| virtual void init(unsigned); | |
| virtual void setup(); | |
| virtual void finish(); | |
| bool clockTick(Cycle_t); | |
| virtual ExternalMaster::Port *getExternalPort( | |
| const std::string &name, ExternalMaster &owner, | |
| const std::string &port_data); | |
| virtual ExternalSlave::Port *getExternalPort( | |
| const std::string &name, ExternalSlave &owner, | |
| const std::string &port_data); | |
| }; | |
| } | |
| } | |
| #endif |