| # Copyright (c) 2021 The Regents of the University of California |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| from ..utils.override import overrides |
| from ..boards.mem_mode import MemMode |
| from .linear_generator_core import LinearGeneratorCore |
| |
| from .abstract_processor import AbstractProcessor |
| from ..boards.abstract_board import AbstractBoard |
| |
| from typing import List |
| |
| |
| class LinearGenerator(AbstractProcessor): |
| def __init__( |
| self, |
| num_cores: int = 1, |
| duration: str = "1ms", |
| rate: str = "100GB/s", |
| block_size: int = 64, |
| min_addr: int = 0, |
| max_addr: int = 32768, |
| rd_perc: int = 100, |
| data_limit: int = 0, |
| ) -> None: |
| super(LinearGenerator, self).__init__( |
| cores=self._create_cores( |
| num_cores=num_cores, |
| duration=duration, |
| rate=rate, |
| block_size=block_size, |
| min_addr=min_addr, |
| max_addr=max_addr, |
| rd_perc=rd_perc, |
| data_limit=data_limit, |
| ) |
| ) |
| """The linear generator |
| |
| This class defines an external interface to create a list of linear |
| generator cores that could replace the processing cores in a board. |
| |
| :param num_cores: The number of linear generator cores to create. |
| :param duration: The number of ticks for the generator to generate |
| traffic. |
| :param rate: The rate at which the synthetic data is read/written. |
| :param block_size: The number of bytes to be read/written with each |
| request. |
| :param min_addr: The lower bound of the address range the generator |
| will read/write from/to. |
| :param max_addr: The upper bound of the address range the generator |
| will read/write from/to. |
| :param rd_perc: The percentage of read requests among all the generated |
| requests. The write percentage would be equal to 100 - rd_perc. |
| :param data_limit: The amount of data in bytes to read/write by the |
| generator before stopping generation. |
| """ |
| |
| def _create_cores( |
| self, |
| num_cores, |
| duration, |
| rate, |
| block_size, |
| min_addr, |
| max_addr, |
| rd_perc, |
| data_limit, |
| ) -> List[LinearGeneratorCore]: |
| """ |
| The helper function to create the cores for the generator, it will use |
| the same inputs as the constructor function. |
| """ |
| return [ |
| LinearGeneratorCore( |
| duration=duration, |
| rate=rate, |
| block_size=block_size, |
| min_addr=min_addr, |
| max_addr=max_addr, |
| rd_perc=rd_perc, |
| data_limit=data_limit, |
| ) |
| for i in range(num_cores) |
| ] |
| |
| @overrides(AbstractProcessor) |
| def incorporate_processor(self, board: AbstractBoard) -> None: |
| board.set_mem_mode(MemMode.TIMING) |
| |
| def start_traffic(self) -> None: |
| """ |
| This function will start the assigned traffic to this generator. |
| """ |
| for core in self.cores: |
| core.start_traffic() |