arch-riscv: rvc instruction is mistaken as branch

Fetch in O3CPU mistakes the normal non-branching compressed
instructions, and regards it as a branch. This issue interrupts
the consecutive instruction stream, thus affecting performance
of cpu front-end.
This fix sets the compressed for PCState during decoding.

Jira Issue:

Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904
Reviewed-by: Jin Cui <>
Reviewed-by: Ayaz Akram <>
Maintainer: Jason Lowe-Power <>
Tested-by: kokoro <>
Reviewed-by: Jason Lowe-Power <>
1 file changed