commit | bf986c2d18370078bd225eeb6f0b7e63cecbdc04 | [log] [tgz] |
---|---|---|
author | Cui Jin <cuijinbird@gmail.com> | Tue Dec 21 23:15:03 2021 +0800 |
committer | Bobby Bruce <bbruce@ucdavis.edu> | Tue Feb 08 19:38:40 2022 +0000 |
tree | b5800f86b8d58dc5bdaf2b93f26018765eabbf28 | |
parent | f554b1a7b56b5889bd5daec6e09eda8c3fbd93d1 [diff] |
arch-riscv: rvc instruction is mistaken as branch Fetch in O3CPU mistakes the normal non-branching compressed instructions, and regards it as a branch. This issue interrupts the consecutive instruction stream, thus affecting performance of cpu front-end. This fix sets the compressed for PCState during decoding. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1137 Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54644 Reviewed-by: Jin Cui <cuijinbird@gmail.com> Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56243 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index 4fbcc64..a02415f 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc
@@ -105,8 +105,10 @@ if (compressed(emi)) { next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2); + next_pc.compressed(true); } else { next_pc.npc(next_pc.instAddr() + sizeof(machInst)); + next_pc.compressed(false); } return decode(emi, next_pc.instAddr());