blob: c93260a96464140460413d2a04d633c7e92f3c27 [file] [log] [blame]
# -*- mode:python -*-
# Copyright (c) 2004-2006 The Regents of The University of Michigan
# Copyright (c) 2020 LabWare
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
Source('decoder.cc', tags='mips isa')
Source('dsp.cc', tags='mips isa')
Source('faults.cc', tags='mips isa')
Source('idle_event.cc', tags='mips isa')
Source('interrupts.cc', tags='mips isa')
Source('isa.cc', tags='mips isa')
Source('linux/se_workload.cc', tags='mips isa')
Source('pagetable.cc', tags='mips isa')
Source('process.cc', tags='mips isa')
Source('remote_gdb.cc', tags='mips isa')
Source('se_workload.cc', tags='mips isa')
Source('tlb.cc', tags='mips isa')
Source('utility.cc', tags='mips isa')
SimObject('MipsDecoder.py', sim_objects=['MipsDecoder'], tags='mips isa')
SimObject('MipsInterrupts.py', sim_objects=['MipsInterrupts'], tags='mips isa')
SimObject('MipsISA.py', sim_objects=['MipsISA'], tags='mips isa')
SimObject('MipsMMU.py', sim_objects=['MipsMMU'], tags='mips isa')
SimObject('MipsSeWorkload.py', sim_objects=['MipsSEWorkload', 'MipsEmuLinux'],
tags='mips isa')
SimObject('MipsTLB.py', sim_objects=['MipsTLB'], tags='mips isa')
SimObject('MipsCPU.py', sim_objects=[], tags='mips isa')
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('O3CPU.py', sim_objects=[], tags='mips isa')
DebugFlag('MipsPRA', tags='mips isa')
ISADesc('isa/main.isa', tags='mips isa')