commit c16b5042997a9247066f4f06d9c59479fc0c169c
author Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Apr 25 10:43:48 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Thu May 02 14:33:22 2019 +0000
tree 02feb3377254f8499617d1e8c285e6d83b974f75
parent 7ad6c8031abd4d0d2d0bb555319399b2b180d073

dev-arm: Take LPIs into account when interacting with CPUIF regs

Previous code was not handling LPIs when it came to
activation/deactivation of interrupts.

Change-Id: Ie38f83c66afdc42132679d7e2e5823990f1710d0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18595
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 577442e..3598f34 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -409,7 +409,8 @@
               int_id = getHPPIR0();
 
               // avoid activation for special interrupts
-              if (int_id < Gicv3::INTID_SECURE) {
+              if (int_id < Gicv3::INTID_SECURE ||
+                  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
                   activateIRQ(int_id, hppi.group);
               }
           } else {
@@ -464,7 +465,8 @@
               int_id = getHPPIR1();
 
               // avoid activation for special interrupts
-              if (int_id < Gicv3::INTID_SECURE) {
+              if (int_id < Gicv3::INTID_SECURE ||
+                  int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
                   activateIRQ(int_id, hppi.group);
               }
           } else {
@@ -778,7 +780,8 @@
           int int_id = val & 0xffffff;
 
           // avoid activation for special interrupts
-          if (int_id >= Gicv3::INTID_SECURE) {
+          if (int_id >= Gicv3::INTID_SECURE &&
+              int_id <= Gicv3::INTID_SPURIOUS) {
               return;
           }
 
@@ -847,7 +850,8 @@
           int int_id = val & 0xffffff;
 
           // avoid deactivation for special interrupts
-          if (int_id >= Gicv3::INTID_SECURE) {
+          if (int_id >= Gicv3::INTID_SECURE &&
+              int_id <= Gicv3::INTID_SPURIOUS) {
               return;
           }
 
@@ -1770,6 +1774,9 @@
         // SPI, distributor
         distributor->activateIRQ(int_id);
         distributor->updateAndInformCPUInterfaces();
+    } else if (int_id >= Gicv3Redistributor::SMALLEST_LPI_ID) {
+        // LPI, Redistributor
+        redistributor->setClrLPI(int_id, false);
     }
 }
 
@@ -1806,7 +1813,8 @@
         distributor->deactivateIRQ(int_id);
         distributor->updateAndInformCPUInterfaces();
     } else {
-        return;
+        // LPI, redistributor, shouldn't deactivate
+        redistributor->updateAndInformCPUInterface();
     }
 }
 

src/dev/arm/gic_v3_redistributor.cc

diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index e22d830..79de7d5 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -854,7 +854,8 @@
     }
 
     if (!new_hppi && cpuInterface->hppi.prio != 0xff &&
-        cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
+        (cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX ||
+         cpuInterface->hppi.intid > SMALLEST_LPI_ID)) {
         distributor->fullUpdate();
     }
 }