mem: Eliminate the Base(Slave|Master)Port classes.
The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.
Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index cd33ef4..8aab513 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -48,7 +48,6 @@
#include "sim/sim_object.hh"
class ThreadContext;
-class BaseMasterPort;
class BaseTLB : public SimObject
{
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0de7f21..bc29c8c 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -64,9 +64,6 @@
#include "params/WriteAllocator.hh"
#include "sim/core.hh"
-class BaseMasterPort;
-class BaseSlavePort;
-
using namespace std;
BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 8794829..ceb356a 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -81,9 +81,7 @@
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-class BaseMasterPort;
class BasePrefetcher;
-class BaseSlavePort;
class MSHR;
class MasterPort;
class QueueEntry;
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 303d1bc..36e11ca 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -51,81 +51,11 @@
#include "base/trace.hh"
#include "sim/sim_object.hh"
-BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
- : Port(name, _id), _baseSlavePort(NULL)
-{
-}
-
-BaseMasterPort::~BaseMasterPort()
-{
-}
-
-BaseSlavePort&
-BaseMasterPort::getSlavePort() const
-{
- if (_baseSlavePort == NULL)
- panic("Cannot getSlavePort on master port %s that is not connected\n",
- name());
-
- return *_baseSlavePort;
-}
-
-void
-BaseMasterPort::bind(Port &peer)
-{
- _baseSlavePort = dynamic_cast<BaseSlavePort *>(&peer);
- fatal_if(!_baseSlavePort, "Attempt to bind port %s to non-master port %s.",
- name(), peer.name());
- Port::bind(peer);
-}
-
-void
-BaseMasterPort::unbind()
-{
- _baseSlavePort = nullptr;
- Port::unbind();
-}
-
-BaseSlavePort::BaseSlavePort(const std::string &name, PortID _id)
- : Port(name, _id), _baseMasterPort(NULL)
-{
-}
-
-BaseSlavePort::~BaseSlavePort()
-{
-}
-
-BaseMasterPort&
-BaseSlavePort::getMasterPort() const
-{
- if (_baseMasterPort == NULL)
- panic("Cannot getMasterPort on slave port %s that is not connected\n",
- name());
-
- return *_baseMasterPort;
-}
-
-void
-BaseSlavePort::bind(Port &peer)
-{
- _baseMasterPort = dynamic_cast<BaseMasterPort *>(&peer);
- fatal_if(!_baseMasterPort, "Attempt to bind port %s to non-slave port %s.",
- name(), peer.name());
- Port::bind(peer);
-}
-
-void
-BaseSlavePort::unbind()
-{
- _baseMasterPort = nullptr;
- Port::unbind();
-}
-
/**
* Master port
*/
MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id)
- : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner)
+ : Port(name, _id), _slavePort(NULL), owner(*_owner)
{
}
@@ -143,7 +73,7 @@
}
// master port keeps track of the slave port
_slavePort = slave_port;
- BaseMasterPort::bind(peer);
+ Port::bind(peer);
// slave port also keeps track of master port
_slavePort->slaveBind(*this);
}
@@ -156,7 +86,7 @@
name());
_slavePort->slaveUnbind();
_slavePort = nullptr;
- BaseMasterPort::unbind();
+ Port::unbind();
}
AddrRangeList
@@ -182,7 +112,7 @@
* Slave port
*/
SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id)
- : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
+ : Port(name, id), _masterPort(NULL), defaultBackdoorWarned(false),
owner(*_owner)
{
}
@@ -195,14 +125,14 @@
SlavePort::slaveUnbind()
{
_masterPort = NULL;
- BaseSlavePort::unbind();
+ Port::unbind();
}
void
SlavePort::slaveBind(MasterPort& master_port)
{
_masterPort = &master_port;
- BaseSlavePort::bind(master_port);
+ Port::bind(master_port);
}
Tick
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 0b589da..0149084 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -60,47 +60,6 @@
class SimObject;
/** Forward declaration */
-class BaseSlavePort;
-
-/**
- * A BaseMasterPort is a protocol-agnostic master port, responsible
- * only for the structural connection to a slave port. The final
- * master port that inherits from the base class must override the
- * bind member function for the specific slave port class.
- */
-class BaseMasterPort : public Port
-{
- protected:
- BaseSlavePort *_baseSlavePort;
-
- BaseMasterPort(const std::string &name, PortID id=InvalidPortID);
- virtual ~BaseMasterPort();
-
- public:
- BaseSlavePort& getSlavePort() const;
- void bind(Port &peer) override;
- void unbind() override;
-};
-
-/**
- * A BaseSlavePort is a protocol-agnostic slave port, responsible
- * only for the structural connection to a master port.
- */
-class BaseSlavePort : public Port
-{
- protected:
- BaseMasterPort *_baseMasterPort;
-
- BaseSlavePort(const std::string &name, PortID id=InvalidPortID);
- virtual ~BaseSlavePort();
-
- public:
- BaseMasterPort& getMasterPort() const;
- void bind(Port &peer) override;
- void unbind() override;
-};
-
-/** Forward declaration */
class SlavePort;
/**
@@ -113,7 +72,7 @@
* The three protocols are atomic, timing, and functional, each with its own
* header file.
*/
-class MasterPort : public BaseMasterPort, public AtomicRequestProtocol,
+class MasterPort : public Port, public AtomicRequestProtocol,
public TimingRequestProtocol, public FunctionalRequestProtocol
{
friend class SlavePort;
@@ -296,7 +255,7 @@
* The three protocols are atomic, timing, and functional, each with its own
* header file.
*/
-class SlavePort : public BaseSlavePort, public AtomicResponseProtocol,
+class SlavePort : public Port, public AtomicResponseProtocol,
public TimingResponseProtocol, public FunctionalResponseProtocol
{
friend class MasterPort;
