| # -*- coding: utf-8 -*- |
| # Copyright (c) 2017 Jason Lowe-Power |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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| |
| """ This file creates a barebones system and executes 'hello', a simple Hello |
| World application. Adds a simple cache between the CPU and the membus. |
| |
| This config file assumes that the x86 ISA was built. |
| """ |
| |
| # import the m5 (gem5) library created when gem5 is built |
| import m5 |
| |
| # import all of the SimObjects |
| from m5.objects import * |
| |
| # create the system we are going to simulate |
| system = System() |
| |
| # Set the clock frequency of the system (and all of its children) |
| system.clk_domain = SrcClockDomain() |
| system.clk_domain.clock = "1GHz" |
| system.clk_domain.voltage_domain = VoltageDomain() |
| |
| # Set up the system |
| system.mem_mode = "timing" # Use timing accesses |
| system.mem_ranges = [AddrRange("512MB")] # Create an address range |
| |
| # Create a simple CPU |
| system.cpu = X86TimingSimpleCPU() |
| |
| # Create a memory bus, a coherent crossbar, in this case |
| system.membus = SystemXBar() |
| |
| # Create a simple cache |
| system.cache = SimpleCache(size="1kB") |
| |
| # Connect the I and D cache ports of the CPU to the memobj. |
| # Since cpu_side is a vector port, each time one of these is connected, it will |
| # create a new instance of the CPUSidePort class |
| system.cpu.icache_port = system.cache.cpu_side |
| system.cpu.dcache_port = system.cache.cpu_side |
| |
| # Hook the cache up to the memory bus |
| system.cache.mem_side = system.membus.cpu_side_ports |
| |
| # create the interrupt controller for the CPU and connect to the membus |
| system.cpu.createInterruptController() |
| system.cpu.interrupts[0].pio = system.membus.mem_side_ports |
| system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports |
| system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports |
| |
| # Create a DDR3 memory controller and connect it to the membus |
| system.mem_ctrl = MemCtrl() |
| system.mem_ctrl.dram = DDR3_1600_8x8() |
| system.mem_ctrl.dram.range = system.mem_ranges[0] |
| system.mem_ctrl.port = system.membus.mem_side_ports |
| |
| # Connect the system up to the membus |
| system.system_port = system.membus.cpu_side_ports |
| |
| # Create a process for a simple "Hello World" application |
| process = Process() |
| # Set the command |
| # grab the specific path to the binary |
| thispath = os.path.dirname(os.path.realpath(__file__)) |
| binpath = os.path.join( |
| thispath, "../../../", "tests/test-progs/hello/bin/x86/linux/hello" |
| ) |
| # cmd is a list which begins with the executable (like argv) |
| process.cmd = [binpath] |
| # Set the cpu to use the process as its workload and create thread contexts |
| system.cpu.workload = process |
| system.cpu.createThreads() |
| |
| system.workload = SEWorkload.init_compatible(binpath) |
| |
| # set up the root SimObject and start the simulation |
| root = Root(full_system=False, system=system) |
| # instantiate all of the objects we've created above |
| m5.instantiate() |
| |
| print("Beginning simulation!") |
| exit_event = m5.simulate() |
| print("Exiting @ tick %i because %s" % (m5.curTick(), exit_event.getCause())) |
