src/python/gem5/components/processors/base_cpu_processor.py

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from .base_cpu_core import BaseCPUCore
from ..boards.mem_mode import MemMode
from ...utils.override import overrides
from ..boards.mem_mode import MemMode
from .abstract_processor import AbstractProcessor
from ..boards.abstract_board import AbstractBoard

from typing import List

from m5.util import warn
from m5.objects import (
    BaseO3CPU,
    BaseMinorCPU,
    BaseAtomicSimpleCPU,
    BaseNonCachingSimpleCPU,
    BaseTimingSimpleCPU,
)


class BaseCPUProcessor(AbstractProcessor):
    """
    A processor constructed from a List of BaseCPUCores.

    This gives gem5 stdlib users a way to create processors containing BaseCPU
    SimObjects. While SimpleProcessor does this by-proxy (the user simply
    specifies the desires CPUType and ISA and the correct BaseCPU
    instantiation is chosen), this Processor allows a more raw passing
    of BaseCPU objects.

    Disclaimer
    ----------

    Multiple cores comprising of different BaseCPU types has not been tested
    and is not officially supported.
    """

    def __init__(self, cores: List[BaseCPUCore]):
        super().__init__(cores=cores)

        if any(core.is_kvm_core() for core in self.get_cores()):
            from m5.objects import KvmVM

            self.kvm_vm = KvmVM()

    @overrides(AbstractProcessor)
    def incorporate_processor(self, board: AbstractBoard) -> None:

        if any(core.is_kvm_core() for core in self.get_cores()):
            board.kvm_vm = self.kvm_vm
            # To get the KVM CPUs to run on different host CPUs
            # Specify a different event queue for each CPU
            for i, core in enumerate(self.cores):
                for obj in core.get_simobject().descendants():
                    obj.eventq_index = 0
                core.get_simobject().eventq_index = i + 1
            board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
        elif isinstance(
            self.cores[0].get_simobject(),
            (BaseTimingSimpleCPU, BaseO3CPU, BaseMinorCPU),
        ):
            board.set_mem_mode(MemMode.TIMING)
        elif isinstance(
            self.cores[0].get_simobject(), BaseNonCachingSimpleCPU
        ):
            board.set_mem_mode(MemMode.ATOMIC_NONCACHING)
        elif isinstance(self.cores[0].get_simobject(), BaseAtomicSimpleCPU):
            if board.get_cache_hierarchy().is_ruby():
                warn(
                    "Using an atomic core with Ruby will result in "
                    "'atomic_noncaching' memory mode. This will skip caching "
                    "completely."
                )
            else:
                board.set_mem_mode(MemMode.ATOMIC)
        else:
            raise NotImplementedError