| // Copyright (c) 2007-2008 The Hewlett-Packard Development Company |
| // Copyright (c) 2011 Mark D. Hill and David A. Wood |
| // All rights reserved. |
| // |
| // The license below extends only to copyright in the software and shall |
| // not be construed as granting a license to any other intellectual |
| // property including but not limited to intellectual property relating |
| // to a hardware implementation of the functionality of the software |
| // licensed hereunder. You may use the software subject to the license |
| // terms below provided that you ensure that this notice is replicated |
| // unmodified and in its entirety in all distributions of the software, |
| // modified or unmodified, in source code or in binary form. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| ////////////////////////////////////////////////////////////////////////// |
| // |
| // Fault Microop |
| // |
| ////////////////////////////////////////////////////////////////////////// |
| |
| def template MicroFaultDeclare {{ |
| class %(class_name)s : public %(base_class)s |
| { |
| private: |
| %(reg_idx_arr_decl)s; |
| |
| public: |
| %(class_name)s(ExtMachInst mach_inst, const char *inst_mnem, |
| uint64_t set_flags, Fault _fault, uint8_t _cc); |
| |
| Fault execute(ExecContext *, Trace::InstRecord *) const override; |
| }; |
| }}; |
| |
| def template MicroFaultExecute {{ |
| Fault |
| %(class_name)s::execute(ExecContext *xc, |
| Trace::InstRecord *traceData) const |
| { |
| %(op_decl)s; |
| %(op_rd)s; |
| if (%(cond_test)s) { |
| // Return the fault we were constructed with. |
| return fault; |
| } else { |
| return NoFault; |
| } |
| } |
| }}; |
| |
| def template MicroFaultConstructor {{ |
| %(class_name)s::%(class_name)s( |
| ExtMachInst mach_inst, const char *inst_mnem, uint64_t set_flags, |
| Fault _fault, uint8_t _cc) : |
| %(base_class)s(mach_inst, "fault", inst_mnem, set_flags, No_OpClass, |
| { _fault }, _cc) |
| { |
| %(set_reg_idx_arr)s; |
| %(constructor)s; |
| } |
| }}; |
| |
| let {{ |
| class Fault(X86Microop): |
| className = "MicroFault" |
| def __init__(self, fault, flags=None): |
| self.fault = fault |
| if flags: |
| if not isinstance(flags, (list, tuple)): |
| raise Exception("flags must be a list or tuple of flags") |
| self.cond = " | ".join(flags) |
| self.className += "Flags" |
| else: |
| self.cond = "0" |
| |
| def getAllocator(self, microFlags): |
| allocator = '''new %(class_name)s(machInst, macrocodeBlock, |
| %(flags)s, %(fault)s, %(cc)s)''' % { |
| "class_name" : self.className, |
| "flags" : self.microFlagsText(microFlags), |
| "fault" : self.fault, |
| "cc" : self.cond} |
| return allocator |
| |
| iop = InstObjParams("fault", "MicroFaultFlags", |
| "X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>", |
| {"code": "", |
| "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \ |
| ecfBit | ezfBit, cc)"}) |
| exec_output = MicroFaultExecute.subst(iop) |
| header_output = MicroFaultDeclare.subst(iop) |
| decoder_output = MicroFaultConstructor.subst(iop) |
| iop = InstObjParams("fault", "MicroFault", |
| "X86ISA::InstOperands<X86ISA::MicroCondBase, X86ISA::FaultOp>", |
| {"code": "", |
| "cond_test": "true"}) |
| exec_output += MicroFaultExecute.subst(iop) |
| header_output += MicroFaultDeclare.subst(iop) |
| decoder_output += MicroFaultConstructor.subst(iop) |
| microopClasses["fault"] = Fault |
| |
| class Halt(X86Microop): |
| className = "MicroHalt" |
| def __init__(self): |
| pass |
| |
| def getAllocator(self, microFlags): |
| return "new X86ISA::MicroHalt(machInst, macrocodeBlock, %s)" % \ |
| self.microFlagsText(microFlags) |
| |
| microopClasses["halt"] = Halt |
| }}; |
| |
| def template MicroFenceOpDeclare {{ |
| class %(class_name)s : public %(base_class)s |
| { |
| private: |
| %(reg_idx_arr_decl)s; |
| |
| public: |
| %(class_name)s(ExtMachInst mach_inst, const char *inst_mnem, |
| uint64_t set_flags); |
| |
| Fault |
| execute(ExecContext *, Trace::InstRecord *) const override |
| { |
| return NoFault; |
| } |
| }; |
| }}; |
| |
| def template MicroFenceOpConstructor {{ |
| %(class_name)s::%(class_name)s( |
| ExtMachInst mach_inst, const char *inst_mnem, uint64_t set_flags) : |
| %(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, |
| set_flags, %(op_class)s) |
| { |
| %(set_reg_idx_arr)s; |
| %(constructor)s; |
| } |
| }}; |
| |
| let {{ |
| class MfenceOp(X86Microop): |
| def __init__(self): |
| self.className = "Mfence" |
| self.mnemonic = "mfence" |
| self.instFlags = "| (1ULL << StaticInst::IsReadBarrier)" + \ |
| "| (1ULL << StaticInst::IsWriteBarrier)" |
| |
| def getAllocator(self, microFlags): |
| allocString = ''' |
| (StaticInstPtr)(new %(class_name)s(machInst, |
| macrocodeBlock, %(flags)s)) |
| ''' |
| allocator = allocString % { |
| "class_name" : self.className, |
| "mnemonic" : self.mnemonic, |
| "flags" : self.microFlagsText(microFlags) + self.instFlags} |
| return allocator |
| |
| microopClasses["mfence"] = MfenceOp |
| }}; |
| |
| let {{ |
| # Build up the all register version of this micro op |
| iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase', |
| {"code" : ""}) |
| header_output += MicroFenceOpDeclare.subst(iop) |
| decoder_output += MicroFenceOpConstructor.subst(iop) |
| # exec_output += BasicExecute.subst(iop) |
| }}; |
| |
| let {{ |
| class SfenceOp(X86Microop): |
| def __init__(self): |
| self.className = "Sfence" |
| self.mnemonic = "sfence" |
| self.instFlags = "| (1ULL << StaticInst::IsWriteBarrier)" |
| |
| def getAllocator(self, microFlags): |
| allocString = ''' |
| (StaticInstPtr)(new %(class_name)s(machInst, |
| macrocodeBlock, %(flags)s)) |
| ''' |
| allocator = allocString % { |
| "class_name" : self.className, |
| "mnemonic" : self.mnemonic, |
| "flags" : self.microFlagsText(microFlags) + self.instFlags} |
| return allocator |
| |
| microopClasses["sfence"] = SfenceOp |
| }}; |
| |
| let {{ |
| # Build up the all register version of this micro op |
| iop = InstObjParams("sfence", "Sfence", 'X86MicroopBase', |
| {"code" : ""}) |
| header_output += MicroFenceOpDeclare.subst(iop) |
| decoder_output += MicroFenceOpConstructor.subst(iop) |
| # exec_output += BasicExecute.subst(iop) |
| }}; |
| |
| let {{ |
| class LfenceOp(X86Microop): |
| def __init__(self): |
| self.className = "Lfence" |
| self.mnemonic = "lfence" |
| self.instFlags = "| (1ULL << StaticInst::IsReadBarrier)" |
| |
| def getAllocator(self, microFlags): |
| allocString = ''' |
| (StaticInstPtr)(new %(class_name)s(machInst, |
| macrocodeBlock, %(flags)s)) |
| ''' |
| allocator = allocString % { |
| "class_name" : self.className, |
| "mnemonic" : self.mnemonic, |
| "flags" : self.microFlagsText(microFlags) + self.instFlags} |
| return allocator |
| |
| microopClasses["lfence"] = LfenceOp |
| }}; |
| |
| let {{ |
| # Build up the all register version of this micro op |
| iop = InstObjParams("lfence", "Lfence", 'X86MicroopBase', |
| {"code" : ""}) |
| header_output += MicroFenceOpDeclare.subst(iop) |
| decoder_output += MicroFenceOpConstructor.subst(iop) |
| # exec_output += BasicExecute.subst(iop) |
| }}; |
| |
| let {{ |
| class SerializeOp(X86Microop): |
| def __init__(self): |
| self.className = "Serialize" |
| self.mnemonic = "serialize" |
| self.instFlags = "| (1ULL << StaticInst::IsSerializeAfter)" |
| |
| def getAllocator(self, microFlags): |
| allocString = ''' |
| (StaticInstPtr)(new %(class_name)s(machInst, |
| macrocodeBlock, %(flags)s)) |
| ''' |
| allocator = allocString % { |
| "class_name" : self.className, |
| "mnemonic" : self.mnemonic, |
| "flags" : self.microFlagsText(microFlags) + self.instFlags} |
| return allocator |
| |
| microopClasses["serialize"] = SerializeOp |
| }}; |
| |
| let {{ |
| # Build up the all register version of this micro op |
| iop = InstObjParams("serialize", "Serialize", 'X86MicroopBase', |
| {"code" : ""}) |
| header_output += MicroFenceOpDeclare.subst(iop) |
| decoder_output += MicroFenceOpConstructor.subst(iop) |
| # exec_output += BasicExecute.subst(iop) |
| }}; |