src/dev/mips/Malta.py

# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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from m5.params import *
from m5.proxy import *

from m5.objects.BadDevice import BadDevice
from m5.objects.Device import BasicPioDevice
from m5.objects.Platform import Platform
from m5.objects.Uart import Uart8250

class MaltaCChip(BasicPioDevice):
    type = 'MaltaCChip'
    cxx_header = "dev/mips/malta_cchip.hh"
    malta = Param.Malta(Parent.any, "Malta")

class MaltaIO(BasicPioDevice):
    type = 'MaltaIO'
    cxx_header = "dev/mips/malta_io.hh"
    time = Param.Time('01/01/2009',
        "System time to use (0 for actual time, default is 1/1/06)")
    year_is_bcd = Param.Bool(False,
            "The RTC should interpret the year as a BCD value")
    malta = Param.Malta(Parent.any, "Malta")
    frequency = Param.Frequency('1024Hz', "frequency of interrupts")

class Malta(Platform):
    type = 'Malta'
    cxx_header = "dev/mips/malta.hh"
    system = Param.System(Parent.any, "system")
    cchip = MaltaCChip(pio_addr=0x801a0000000)
    io = MaltaIO(pio_addr=0x801fc000000)
    uart = Uart8250(pio_addr=0xBFD003F8)

    # Attach I/O devices to specified bus object.  Can't do this
    # earlier, since the bus object itself is typically defined at the
    # System level.
    def attachIO(self, bus):
        self.cchip.pio = bus.mem_side_ports
        self.io.pio = bus.mem_side_ports
        self.uart.pio = bus.mem_side_ports