This release has 500 contributions from 48 unique contributors and marks our second major release of 2022. This release incorporates several new features, improvements, and bug fixes for the computer architecture reserach community.
See below for more details!
scons build/ALL/gem5.opt. This will use the Ruby MESI_Two_Level cache coherence protocol by default, to use other protocols: scons build/ALL/gem5.opt PROTOCOL=<other protocol>. The classic cache system may continue to be used regardless as to which Ruby cache coherence protocol is compiled.m5 Python module now includes functions to set exit events are particular simululation ticks:RiscvMatched board as part of the gem5 stdlib. This board is modeled after the HiFive Unmatched board and may be used to emulate its behavior. See “configs/example/gem5_library/riscv-matched-fs.py” and “configs/example/gem5_library/riscv-matched-hello.py” for examples using this board.set_workload function. For example, set_workload(Workload("x86-ubuntu-18.04-boot")) sets the board to use the “x86-ubuntu-18.04-boot” workload. This workload specifies a boot consisting of the Linux 5.4.49 kernel then booting an Ubunutu 18.04 disk image, to exit upon booting. Workloads are agnostic to underlying gem5 design and, via the gem5-resources infrastructure, will automatically retrieve all necessary kernels, disk-images, etc., necessary to execute. Examples of using gem5 Workloads can be found in “configs/example/gem5_library/x86-ubuntu-ruby.py” and “configs/example/gem5_library/riscv-ubuntu-run.py”.git commit. Users may install pre-commit by running ./util/pre-commit-install.sh. Passing these checks is a requirement to submit code to gem5 so installation is strongly advised.ArmBoard now supports Ruby caches.HBM2Stack has been added to the gem5 stdlib as a memory component.MinorCPU has been fully incorporated into the gem5 Standard Library.HygonGenuine. This is due to newer versions of GLIBC being more strict about checking current system's supported features. The previous value, M5 Simulator, is not recognized as a valid vendor string and therefore GLIBC returns an error._connect_things funciton call has been moved from the AbstractBoard's constructor to be run as board pre-instantiation process. This is to overcome instances where stdlib components (memory, processor, and cache hierarhcy) require Board information known only after its construction. This change breaks cases where a user utilizes the stdlib AbstractBoard but does not use the stdlib Simulator module. This can be fixed by adding the _pre_instantiate function before m5.instantiate. An exception has been added which explains this fix, if this error occurs.Simulator module. Setting of checkpoints via the stdlib’s “set_workload” functions is now deprecated and will be removed in future releases of gem5.Trace has been renamed trace to conform to the gem5 style guide.TARGET_ISA variable has been replaced with USE_$(ISA) variables. For example, if a build contains both the X86 and ARM ISAs the USE_X86 and USE_ARM variables will be set.open(2) flag values. These values have been fixed.sim_quantum value was set for all cores when using the Standard Library. This caused issues when setting exit events at a particular tick as it resulted in the exit being off by sim_quantum. As such, the sim_quantum value is only when using KVM cores.VExpress_GEM5_Foundation fixed.SwitchableProcessor processor has been fixed to allow switching to a KVM core. Previously the SwitchableProcessor only allowed a user to switch from a KVM core to a non-KVM core.Simulator module may be utilized in gem5.get_simstats function has been added to access statistics from the Simulator module.print(simstats.board.core.some_integer).m5 utility has been expanded to include “workbegin” and “workend” annotations. This can be added with m5 workbegin and m5 workend.PrivateL1SharedL2CacheHierarchy has been added to the Standard Library.GEM5_USE_PROXY environment variable has been added. This allows users to specify a socks5 proxy server to use when obtaining gem5 resources and the resources.json file. It uses the format <host>:<port>.set_se_binary_workload function now allows for the passing of input parameters to a binary workload.[HOTFIX] This hotfix contains a set of critical fixes to be applied to gem5 v22.0. This hotfix:
requires functions in AbstractProcessor and AbstractGeneratorCore. These requires were causing errors when running generators with any ISA other than NULL.set_se_binary_workload function to exit on Exit Events (work items) by default.getAddrRanges function to the HBMCtrl. This ensures the XBar connected to the controller can see the address ranges covered by both pseudo channels.[HOTFIX] Fixes relative import in “src/python/gem5/components/processors/simple_core.py”.
The import from python.gem5.utils.requires import requires in v22.0.0.0 of gem5 is incorrect as it causes problems when executing gem5 binaries in certain directories (python isn't necessary included). To resolve this, this import has been changed to from ...utils.requires imports requires. This should work in all supported use-cases.
gem5 version 22.0 has been slightly delayed, but we a have a very strong release! This release has 660 changes from 48 unique contributors. While there are not too many big ticket features, the community has done a lot to improve the stablity and add bugfixes to gem5 over this release. That said, we have a few cool new features like full system GPU support, a huge number of Arm improvements, and an improved HBM model.
See below for more details!
The following RISCV instructions have been added to gem5's RISC-V ISA:
The gem5 standard library's downloader has been re-engineered to more efficiently obtain the resources.json file. It is now cached instead of retrieved on each resource retrieval.
The resources.json directory has been moved to a more permament URL at http://resources.gem5.org/resources.json.
Tests have also been added to ensure the resources module continues to function correctly.
The gem5 in SystemC has been revamped to accomodate new research needs. These changes include stability improvements and bugs fixes. The gem5 testing suite has also been expanded to include gem5 in SystemC tests.
Users may now simulate an AMD GPU device in full system mode using the ROCm 4.2 compute stack. Until v21.2, gem5 only supported GPU simulation in Syscall-Emulation mode with ROCm 4.0. See src/gpu-fs/README.md in gem5-resources and example scripts in configs/example/gpufs/ for example scripts which run GPU full system simulations.
A GPU Ruby random tester has been added to help validate the correctness of the CPU and GPU Ruby coherence protocols as part of every kokoro check-in. This helps validate the correctness of the protocols before new changes are checked in. Currently the tester focuses on the protocols used with the GPU, but the ideas are extensible to other protocols. The work is based on “Autonomous Data-Race-Free GPU Testing”, IISWC 2019, Tuan Ta, Xianwei Zhang, Anthony Gutierrez, and Bradford M. Beckmann.
Via this change, an ARM Board, ArmBoard, has been added to the gem5 standard library. This allows for an ARM system to be run using the gem5 stdlib components.
An example gem5 configuration script using this board can be found in configs/example/gem5_library/arm-ubuntu-boot-exit.py.
createAddrRanges now supports NUMA configurationsWhen the system is configured for NUMA, it has multiple memory ranges, and each memory range is mapped to a corresponding NUMA node. For this, the change enables createAddrRanges to map address ranges to only a given HNFs.
Jira ticker here: https://gem5.atlassian.net/browse/GEM5-1187.
For instance, the O3CPU is now the X86O3CPU and ArmO3CPU, etc. This requires a number of changes if you have your own CPU models. See https://gem5-review.googlesource.com/c/public/gem5/+/52490 for details.
Additionally, this requires changes in any configuration script which inherits from the old CPU types.
In many cases, if there is only a single ISA compiled the old name will still work. However, this is not 100% true.
Finally, CPU_MODELS is no longer a parameter in build_opts/. Now, if you want to compile a CPU model for a particular ISA you will have to add a new file for the CPU model in the arch/ directory.
If you have any specialized CPU models or any ISAs which are not in the mainline, expect many changes when rebasing on this release.
initiateSpecialMemCmd renamed to initiateMemMgmtCmd to generalize to other command beyond HTM (e.g., DVM/TLBI)OperandDesc class added (e.g., see https://gem5-review.googlesource.com/c/public/gem5/+/49731)TheISA have been removedandIsCallflags for RISC-V jump instructions by defining a newJumpConstructor` in “standard.isa”. Jira Ticket here: https://gem5.atlassian.net/browse/GEM5-1139.env in the SConscript files now requires you to use env['CONF'] to access them. Anywhere that env['<VARIABLE>'] appeared should noe be env['CONF']['<VARIABLE>']gem5.build directory[HOTFIX] In order to ensure v21 of gem5 remains compatible with future changes, the gem5 stdlib downloader has been updated to obtain the resources.json file from https://resources.gem5.org/resources.json. As this domain is under the gem5 project control, unlike the previous googlesource URL, we can ensure longer-term stability. The fix also ensures the downloader can parse plain-text JSON and base64 encoding of the resources.json file.
Version 21.2.1 is a minor gem5 release consisting of bug fixes. The 21.2.1 release:
All SimObject declarations in SConscript files now require a sim_objects parameter which should list all SimObject classes declared in that file which need c++ wrappers. Those are the SimObject classes which have a type attribute defined.
Also, there is now an optional enums parameter which needs to list all of the Enum types defined in that SimObject file. This should technically only include Enum types which generate c++ wrapper files, but currently all Enums do that so all Enums should be listed.
Previous release had an alpha release of the “components library.” This has now been wrapped in a larger “standard library”.
The gem5 standard library is a Python package which contains the following:
SingleChannelDDR3_1600) and others are parameterized. Components can be combined together onto boards which can be simulated.components. This release has a “demo” board to show an example of how to use the prebuilt systems.Examples of using the gem5 standard library can be found in configs/example/gem5_library/. The source code is found under src/python/gem5.
We now support gem5 cores connected to SST memory system for gem5 full system mode. This has been tested for RISC-V and Arm. See ext/sst/README.md for details.
LupIO devices were developed by Prof. Joel Porquet-Lupine as a set of open-source I/O devices to be used for teaching. They were designed to model a complete set of I/O devices that are neither too complex to teach in a classroom setting, or too simple to translate to understanding real-world devices. Our collection consists of a real-time clock, random number generator, terminal device, block device, system controller, timer device, programmable interrupt controller, as well as an inter-processor interrupt controller. A more detailed outline of LupIO can be found here: https://luplab.cs.ucdavis.edu/assets/lupio/wcae21-porquet-lupio-paper.pdf. Within gem5, these devices offer the capability to run simulations with a complete set of I/O devices that are both easy to understand and manipulate.
The initial implementation of the LupIO devices are for the RISC-V ISA. However, they should be simple to extend to other ISAs through small source changes and updating the SConscripts.
[HOTFIX] A commit introduced std::vector with resize() to initialize all storages. This caused data duplication in statistics and broke the Vector statistics. This hotfix initializes using loops which fixes the broken statistics.
[HOTFIX] A “‘deprecated’ attribute directive ignored” warning was being thrown frequently when trying to build v21.1.0.0. While this issue did not break the build, it made reading the build output difficult and caused confused. As such a patch has been applied to fix this issue.
Since v21.0 we have received 780 commits with 48 unique contributors, closing 64 issues on our Jira Issue Tracker. In addition to our first gem5 minor release, we have included a range of new features, and API changes which we outline below.
The purpose of the gem5 components library is to provide gem5 users a standard set of common and useful gem5 components, pre-built, to add to their experiments. The gem5 components library adopts a modular architecture design so components may be easily added, removed, and extended, as needed.
Examples of using the gem5 components library can be found in configs/example/components-library.
Important Disclaimer: This is a pre-alpha release. The purpose of this release is to get community feedback. Though some testing has been done, we expect regular fixes and improvements until the library reaches a stable state. A Jira Ticket outlining TODOs and known bugs can be found at https://gem5.atlassian.net/browse/GEM5-648.
ROCm 4.0 is now officially supported.
gfx801 (Carrizo) and gfx803 (Fiji) are both supported and tested with the gem5-resources applications.
Better scoreboarding support has been added. This reduces stalls by up to 42%.
Accuracy and coverage stats have been added for prefetcher caches. Accuracy is defined as the ratio of the number of prefetch requests counted as useful over the total number of prefetch requests issued. Coverage is defined as the ratio of the number of prefetch requests counted as useful over the number of useful prefetch request plus the remaining demand misses.
The POWER 64-bit ISA is now supported in Syscall Execution mode.
gem5 now supports simulation of RISC-V Physical Memory Protection (PMP). Simulations can boot and run Keystone and Eyrie.
The gem5 replacement policies framework now supports more complex algorithms. It now allows using addresses, PC, and other information within a policy.
Note: Assuming this information is promptly available at the cache may be unrealistic.
Classes that handle set dueling have been created (Dueler and DuelingMonitor). They can be used in conjunction with different cache policies. A replacement policy that uses it has been added for guidance.
gem5 is now compilable and runnable on a RISC-V host system.
Deprecation MACROS have been added for deprecating namespaces (GEM5_DEPRECATED_NAMESPACE), and deprecating other MACROs (GEM5_DEPRECATED_MACRO).
Note: For technical reasons, using old macros won't produce any deprecation warnings.
Snake case has been adopted as the new convention for name spaces. As a consequence, multiple namespaces have been renamed:
Minor -> minorLoader -> loaderStats -> statisticsEnums -> enumsNet -> networkingProbePoints -> probingContextSwitchTaskId -> context_switch_task_idPrefetcher -> prefetchEncoder -> encoderCompressor -> compressionQoS -> qosReplacementPolicy -> replacement_policyMouse -> mouseKeyboard -> keyboardInt -> as_intFloat -> as_floatFastModel -> fastmodelGuestABI -> guest_abiLockedMem -> locked_memDeliveryMode -> delivery_modePseudoInst -> pseudo_instDecodeCache -> decode_cacheBitfieldBackend -> bitfield_backendFreeBSD -> free_bsdLinux -> linuxUnits -> unitsSimClock -> sim_clockBloomFilter -> bloom_filterX86Macroop -> x86_macroopConditionTests -> condition_testsIntelMP -> intelmpSMBios -> smbiosRomLables -> rom_labelsSCMI -> scmiiGbReg -> igbregPs2 -> ps2CopyEngineReg -> copy_engine_regTxdOp -> txd_opSinic -> sinicDebug -> debugIn addition some other namespaces were added:
gem5::ruby, for Ruby-related filesgem5::ruby::garnet, for garnet-related filesgem5::o3, for the O3-cpu's related filesgem5::memory, for files related to memoriesFinally, the m5 namespace has been renamed gem5.
base/compiler.hhThe MACROs in base/compiler.hh of the form M5_* have been deprecated and replaced with macros of the form GEM5_*, with some other minor name adjustments.
MemObject simobject had been marked for deprecation and has now been officially removed from the gem5 codebase.
GCC version 5 and 6 are no longer supported. GCC 7 is now the minimum GCC compiler version supported. This changes allows has allowed us to move to the C++17 standard for development.
In addition, the minimum Clang version has increased to 6, and Clang 10 and 11 are now officially supported.
Version 21.0.1 is a minor gem5 release consisting of bug fixes. The 21.0.1 release:
config.ini.from_kelvin function.SLICC_HTML=True.errno was incorrectly put as ennro.--restore-simpoint-checkpoint flag default to “False” instead of the ambiguous “None”.scx_get_parameter_list for ARM fast models.--with-lto flag. The --no-lto flag has been removed.Version 21.0 marks one full year of gem5 releases, and on this anniversary, I think we have some of the biggest new features yet! This has been a very productive release with 100 issues, over 813 commits, and 49 unique contributors.
This new protocol provides a single cache controller that can be reused at multiple levels of the cache hierarchy and configured to model multiple instances of MESI and MOESI cache coherency protocols. This implementation is based of Arm’s AMBA 5 CHI specification and provides a scalable framework for the design space exploration of large SoC designs.
See the gem5 documentation for more details. There is also a gem5 blog post on this new protocol as well.
In previous releases, this model was only partially supported. As of gem5 21.0, this model has been fully integrated and is tested nightly. This model currently only works in syscall emulation mode and requires using the gcn docker container to get the correct version of the ROCm stack. More information can be found in this blog post.
With this full support, we are also providing many applications as well. See gem5-resources for more information.
The RISC-V model in gem5 can now boot unmodified Linux! Additionally, we have implemented DTB generation and support the Berkeley Boot Loader as the stage 1 boot loader. We have also released a set of resources for you to get started: https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/develop/src/riscv-fs/
There are multiple places where the developers have reduced boilerplate.
create() functions! Previously, every SimObject required a <SimObjectParams>::create() function to be manually defined. Forgetting to do this resulted in confusing errors. Now, this function is created for you automatically. You can still override it if you need to handle any special cases.params(): Rather than defining a typedef and the params() function for every SimObject, you can now use the PARAMS macro.See http://doxygen.gem5.org/release/current/classSimObject.html#details for more details on these two API changes.
Group) is still supported, but it is now deprecated.Group API, it may not be automatically dumped using new stat APIs (e.g., the Python API).StaticInst type[HOTFIX] This hotfix release fixes three known bugs:
src/python/m5/util/convert.py incorrectly stated kibibytes as ‘kiB’ instead of ‘KiB’. This has been fixed.num_l2chaches_per_cluster and num_cpus_per_cluster were cast to floats in configs/ruby/MESI_Three_Level_HTM.py, which caused errors. This has been fixed so they are correctly cast to integers.[HOTFIX] gem5 was failing to build with SCons 4.0.1 and 4.1.0. This hotfix makes the necessary changes to site_scons/site_tools/default.py for gem5 to compile successfully on these versions of SCons.
[HOTFIX] A patch was apply to fix an error where booting Linux stalled when using the ARM ISA. This fix adds the parameter have_vhe to enable FEAT_VHE on demand, and is disabled by default to resolve this issue.
[HOTFIX] This hotfix release fixes known two bugs:
[HOTFIX] A patch was applied to fix the Garnet network interface stats. Previously, the flit source delay was computed using both tick and cycles. This bug affected the overall behavior of the Garnet Network Model.
Thank you to everyone that made this release possible! This has been a very productive release with 150 issues, over 650 commits (a 25% increase from the 20.0 release), and 58 unique contributors (a 100% increase!).
We are no longer using the “master” branch. Instead, we will have two branches:
We suggest all users use the stable (default) branch. However, to contribute your fixes and new changes to gem5, it should be contributed to the develop branch. See CONTRIBUTING.md for more details.
gem5 has also implemented a project code of conduct. See the CODE-OF-CONDUCT.md file for details. In the code of conduct “we pledge to act and interact in ways that contribute to an open, welcoming, diverse, inclusive, and healthy community.”
You can find details about this on the gem5 blog or Wendy's talks on YouTube: Talk on new interface and NVM and the talk on LPDDR5
SimpleMemory is no longer a drop-in replacement for a DRAM-based memory controller.You can find details about this on the gem5 blog and Srikant's talk on YouTube.
You can find details on the Jira issue
MESI_Three_Level_HTM Ruby protocol, and it is only implemented in Ruby.See http://www.gem5.org/documentation/general_docs/building for gem5's current dependencies.
MasterPort -> RequestorPort SlavePort -> ResponsePort xbar.slave -> xbar.cpu_side xbar.master -> xbar.mem_side MasterId -> RequestorId
tests/ directory in mainline gem5.setCPU to setThreadContext in InterruptsCompressor namespace.Callback class was removed and replaced with C++ lambdas.[HOTFIX] When using the ARM ISA, gem5 could crash when a guest tried to call m5ops. This was due to m5ops_base being incorrectly declared in src/arch/arm/ArmSystem.py. A fix was applied to remove this declaration.
[HOTFIX] A patch was applied to fix the RubyPrefetcher with MESI_Three_Level. Prior to this fix a segfault occurred.
[HOTFIX] A fix was applied to stop incorrect clock frequences being reported due to rounding errors.
Welcome to our first “official” gem5 release! gem5 v19.0.0.0 was a “test” release, but this one has release notes, so it must be official!
Thank you to everyone that made this release possible! This has been a very productive release with over 70 issues closed, over 500 commits, and 31 unique contributors. Below are some of the highlights, though I‘m sure I’ve missed some important changes.
scons build/<arch>/out/m5, not make.LinuxX86System or similar SimObject).System are now parameters of the Workload (see src/sim/Workload.py).LinuxX86System are now part of X86FsLinux which is now the workload parameter of the System SimObject.tests/main.py, except for the unittests.--disk-image argument to fs.py is now optional.M5_PATH, but the name of the disk image must be specified.queueMemory is now enqueue.queueMemoryRead and queueMemoryWrite with enqueue to another “special” message buffer named memQueue.*Prefetcher to Prefetcher::*