commit c99d192690f2bd4bd9aec6b6ae717b949c9409ec
author Luming Wang <wlm199558@126.com> Wed Nov 24 12:35:17 2021 +0800
committer Luming Wang <wlm199558@126.com> Thu Nov 25 06:02:27 2021 +0000
tree c965f0d0a2226237a7a813889bf3ea93b09472bd
parent 8ef0f3067316dfea7cf70790e47fec1a735bc197

arch-riscv: fix inUserMode

The original inUserMode() simply returns true. However, it should
check whether the processor's current privilege level is PRV_U.

Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53184
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/isa.cc

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e26b6fa..0358889 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -205,6 +205,11 @@
     clear();
 }
 
+bool ISA::inUserMode() const
+{
+    return miscRegFile[MISCREG_PRV] == PRV_U;
+}
+
 void
 ISA::copyRegsFrom(ThreadContext *src)
 {

src/arch/riscv/isa.hh

diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 6435b74..143cc69 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -98,7 +98,7 @@
     int flattenCCIndex(int reg) const { return reg; }
     int flattenMiscIndex(int reg) const { return reg; }
 
-    bool inUserMode() const override { return true; }
+    bool inUserMode() const override;
     void copyRegsFrom(ThreadContext *src) override;
 
     void serialize(CheckpointOut &cp) const override;