src/mem/tport.cc

/*
 * Copyright (c) 2012 ARM Limited
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 * Copyright (c) 2006 The Regents of The University of Michigan
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 * met: redistributions of source code must retain the above copyright
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#include "mem/tport.hh"
#include "sim/sim_object.hh"

SimpleTimingPort::SimpleTimingPort(const std::string& _name,
                                   SimObject* _owner) :
    QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
{
}

void
SimpleTimingPort::recvFunctional(PacketPtr pkt)
{
    if (!respQueue.trySatisfyFunctional(pkt)) {
        // do an atomic access and throw away the returned latency
        recvAtomic(pkt);
    }
}

bool
SimpleTimingPort::recvTimingReq(PacketPtr pkt)
{
    // the SimpleTimingPort should not be used anywhere where there is
    // a need to deal with snoop responses and their flow control
    // requirements
    if (pkt->cacheResponding())
        panic("SimpleTimingPort should never see packets with the "
              "cacheResponding flag set\n");

    bool needsResponse = pkt->needsResponse();
    Tick latency = recvAtomic(pkt);
    // turn packet around to go back to requester if response expected
    if (needsResponse) {
        // recvAtomic() should already have turned packet into
        // atomic response
        assert(pkt->isResponse());
        schedTimingResp(pkt, curTick() + latency);
    } else {
        // queue the packet for deletion
        pendingDelete.reset(pkt);
    }

    return true;
}