commit ccdec1b11d404b3f5a2be95192fd4306bb459ccf
author Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Jun 28 14:21:11 2022 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Jul 05 08:45:01 2022 +0000
tree 50c7ac770104e88acae7e0368df0efba7d9d26bf
parent 343f7b7bf667956cc0b62ff7ebdcdcc9363a5470

arch-arm: Do not trap SIMD insts to EL1 if in VHE host

Change-Id: I4ea326eead1aec1e013280b599c57f2202901625
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60971
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/insts/static_inst.cc

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 4367920..ba0e1cf 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014, 2016-2020 ARM Limited
+ * Copyright (c) 2010-2014, 2016-2020,2022 Arm Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -715,8 +715,9 @@
                                        CPSR cpsr, CPACR cpacr) const
 {
     const ExceptionLevel el = currEL(tc);
-    if ((el == EL0 && cpacr.fpen != 0x3) ||
-        (el == EL1 && !(cpacr.fpen & 0x1)))
+    if (((el == EL0 && cpacr.fpen != 0x3) ||
+        (el == EL1 && !(cpacr.fpen & 0x1))) &&
+        !ELIsInHost(tc, el))
         return advSIMDFPAccessTrap64(EL1);
 
     return checkFPAdvSIMDTrap64(tc, cpsr);