blob: eb4aaa7bf198d4bf643ded44b259a4b7904952d9 [file] [log] [blame]
# Copyright (c) 2018 ARM Limited
# All rights reserved.
#
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# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
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#
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# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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from m5.params import *
from m5.objects.ClockedObject import ClockedObject
class MemDelay(ClockedObject):
type = "MemDelay"
cxx_header = "mem/mem_delay.hh"
cxx_class = "gem5::MemDelay"
abstract = True
mem_side_port = RequestPort(
"This port sends requests and receives responses"
)
master = DeprecatedParam(
mem_side_port, "`master` is now called `mem_side_port`"
)
cpu_side_port = ResponsePort(
"This port receives requests and sends responses"
)
slave = DeprecatedParam(
cpu_side_port, "`slave` is now called `cpu_side_port`"
)
class SimpleMemDelay(MemDelay):
type = "SimpleMemDelay"
cxx_header = "mem/mem_delay.hh"
cxx_class = "gem5::SimpleMemDelay"
read_req = Param.Latency("0t", "Read request delay")
read_resp = Param.Latency("0t", "Read response delay")
write_req = Param.Latency("0t", "Write request delay")
write_resp = Param.Latency("0t", "Write response delay")