src/mem/SerialLink.py

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# Copyright (c) 2015 The University of Bologna
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from m5.params import *
from m5.objects.ClockedObject import ClockedObject

# SerialLink is a simple variation of the Bridge class, with the ability to
# account for the latency of packet serialization.


class SerialLink(ClockedObject):
    type = "SerialLink"
    cxx_header = "mem/serial_link.hh"
    cxx_class = "gem5::SerialLink"

    mem_side_port = RequestPort(
        "This port sends requests and receives responses"
    )
    master = DeprecatedParam(
        mem_side_port, "`master` is now called `mem_side_port`"
    )
    cpu_side_port = ResponsePort(
        "This port receives requests and sends responses"
    )
    slave = DeprecatedParam(
        cpu_side_port, "`slave` is now called `cpu_side_port`"
    )
    req_size = Param.Unsigned(16, "The number of requests to buffer")
    resp_size = Param.Unsigned(16, "The number of responses to buffer")
    delay = Param.Latency("0ns", "The latency of this serial_link")
    ranges = VectorParam.AddrRange(
        [AllMemory], "Address ranges to pass through the serial_link"
    )
    # Bandwidth of the serial link is determined by the clock domain which the
    #  link belongs to and the number of lanes:
    num_lanes = Param.Unsigned(
        1,
        "Number of parallel lanes inside the seriallink. (aka. lane width)",
    )
    link_speed = Param.UInt64(
        1,
        "Gb/s Speed of each parallel lane inside the"
        "serial link. (aka. lane speed)",
    )