| |
| ---------- Begin Simulation Statistics ---------- |
| host_inst_rate 1110947 # Simulator instruction rate (inst/s) |
| host_mem_usage 261416 # Number of bytes of host memory used |
| host_seconds 56.81 # Real time elapsed on the host |
| host_tick_rate 32921847339 # Simulator tick rate (ticks/s) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| sim_insts 63114046 # Number of instructions simulated |
| sim_seconds 1.870335 # Number of seconds simulated |
| sim_ticks 1870335151500 # Number of ticks simulated |
| system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits |
| system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses |
| system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses |
| system.cpu0.dcache.ReadReq_accesses 8975647 # number of ReadReq accesses(hits+misses) |
| system.cpu0.dcache.ReadReq_hits 7292074 # number of ReadReq hits |
| system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses |
| system.cpu0.dcache.ReadReq_misses 1683573 # number of ReadReq misses |
| system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) |
| system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits |
| system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses |
| system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses |
| system.cpu0.dcache.WriteReq_accesses 5746071 # number of WriteReq accesses(hits+misses) |
| system.cpu0.dcache.WriteReq_hits 5372265 # number of WriteReq hits |
| system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses |
| system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses |
| system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu0.dcache.avg_refs 6.625595 # Average number of references to valid blocks. |
| system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| system.cpu0.dcache.demand_accesses 14721718 # number of demand (read+write) accesses |
| system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency |
| system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu0.dcache.demand_hits 12664339 # number of demand (read+write) hits |
| system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles |
| system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses |
| system.cpu0.dcache.demand_misses 2057379 # number of demand (read+write) misses |
| system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles |
| system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses |
| system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses |
| system.cpu0.dcache.fast_writes 0 # number of fast writes performed |
| system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu0.dcache.overall_accesses 14721718 # number of overall (read+write) accesses |
| system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency |
| system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu0.dcache.overall_hits 12664339 # number of overall hits |
| system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles |
| system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses |
| system.cpu0.dcache.overall_misses 2057379 # number of overall misses |
| system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits |
| system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles |
| system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses |
| system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses |
| system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu0.dcache.replacements 1978971 # number of replacements |
| system.cpu0.dcache.sampled_refs 1979483 # Sample count of references to valid blocks. |
| system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu0.dcache.tagsinuse 504.827578 # Cycle average of tags in use |
| system.cpu0.dcache.total_refs 13115252 # Total number of references to valid blocks. |
| system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. |
| system.cpu0.dcache.writebacks 396793 # number of writebacks |
| system.cpu0.dtb.accesses 698037 # DTB accesses |
| system.cpu0.dtb.acv 251 # DTB access violations |
| system.cpu0.dtb.hits 15082956 # DTB hits |
| system.cpu0.dtb.misses 7805 # DTB misses |
| system.cpu0.dtb.read_accesses 508987 # DTB read accesses |
| system.cpu0.dtb.read_acv 152 # DTB read access violations |
| system.cpu0.dtb.read_hits 9148379 # DTB read hits |
| system.cpu0.dtb.read_misses 7079 # DTB read misses |
| system.cpu0.dtb.write_accesses 189050 # DTB write accesses |
| system.cpu0.dtb.write_acv 99 # DTB write access violations |
| system.cpu0.dtb.write_hits 5934577 # DTB write hits |
| system.cpu0.dtb.write_misses 726 # DTB write misses |
| system.cpu0.icache.ReadReq_accesses 57190139 # number of ReadReq accesses(hits+misses) |
| system.cpu0.icache.ReadReq_hits 56305276 # number of ReadReq hits |
| system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses |
| system.cpu0.icache.ReadReq_misses 884863 # number of ReadReq misses |
| system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu0.icache.avg_refs 63.637672 # Average number of references to valid blocks. |
| system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| system.cpu0.icache.demand_accesses 57190139 # number of demand (read+write) accesses |
| system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency |
| system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu0.icache.demand_hits 56305276 # number of demand (read+write) hits |
| system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles |
| system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses |
| system.cpu0.icache.demand_misses 884863 # number of demand (read+write) misses |
| system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles |
| system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses |
| system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses |
| system.cpu0.icache.fast_writes 0 # number of fast writes performed |
| system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu0.icache.overall_accesses 57190139 # number of overall (read+write) accesses |
| system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency |
| system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu0.icache.overall_hits 56305276 # number of overall hits |
| system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles |
| system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses |
| system.cpu0.icache.overall_misses 884863 # number of overall misses |
| system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits |
| system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles |
| system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses |
| system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses |
| system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu0.icache.replacements 884267 # number of replacements |
| system.cpu0.icache.sampled_refs 884779 # Sample count of references to valid blocks. |
| system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use |
| system.cpu0.icache.total_refs 56305276 # Total number of references to valid blocks. |
| system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. |
| system.cpu0.icache.writebacks 0 # number of writebacks |
| system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles |
| system.cpu0.itb.accesses 3858846 # ITB accesses |
| system.cpu0.itb.acv 127 # ITB acv |
| system.cpu0.itb.hits 3855361 # ITB hits |
| system.cpu0.itb.misses 3485 # ITB misses |
| system.cpu0.kern.callpal 183273 # number of callpals executed |
| system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed |
| system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed |
| system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed |
| system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed |
| system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed |
| system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed |
| system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed |
| system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed |
| system.cpu0.kern.callpal_swpipl 168018 91.68% 93.82% # number of callpals executed |
| system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed |
| system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed |
| system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed |
| system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed |
| system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed |
| system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed |
| system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed |
| system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed |
| system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| system.cpu0.kern.inst.hwrei 197102 # number of hwrei instructions executed |
| system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed |
| system.cpu0.kern.ipl_count 174851 # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_count_31 101696 58.16% 100.00% # number of times we switched to this ipl |
| system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl |
| system.cpu0.kern.ipl_ticks 1870334944000 # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks_0 1853125190500 99.08% 99.08% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_ticks_31 17106650000 0.91% 100.00% # number of cycles we spent at this ipl |
| system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.ipl_used_31 0.684599 # fraction of swpipl calls that actually changed the ipl |
| system.cpu0.kern.mode_good_kernel 1156 |
| system.cpu0.kern.mode_good_user 1157 |
| system.cpu0.kern.mode_good_idle 0 |
| system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches |
| system.cpu0.kern.mode_switch_user 1157 # number of protection mode switches |
| system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches |
| system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches |
| system.cpu0.kern.mode_switch_good_kernel 0.163047 # fraction of useful protection mode switches |
| system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches |
| system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches |
| system.cpu0.kern.mode_ticks_kernel 1869377939000 99.95% 99.95% # number of ticks spent at the given mode |
| system.cpu0.kern.mode_ticks_user 957004000 0.05% 100.00% # number of ticks spent at the given mode |
| system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| system.cpu0.kern.swap_context 3762 # number of times the context was actually changed |
| system.cpu0.kern.syscall 226 # number of syscalls executed |
| system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed |
| system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed |
| system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed |
| system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed |
| system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed |
| system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed |
| system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed |
| system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed |
| system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed |
| system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed |
| system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed |
| system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed |
| system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed |
| system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed |
| system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed |
| system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed |
| system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed |
| system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed |
| system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed |
| system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed |
| system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed |
| system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed |
| system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed |
| system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed |
| system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed |
| system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed |
| system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed |
| system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed |
| system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed |
| system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed |
| system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles |
| system.cpu0.numCycles 3740670191 # number of cpu cycles simulated |
| system.cpu0.num_insts 57182083 # Number of instructions executed |
| system.cpu0.num_refs 15322406 # Number of memory references |
| system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits |
| system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses |
| system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses |
| system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) |
| system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits |
| system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses |
| system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses |
| system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) |
| system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits |
| system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses |
| system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses |
| system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) |
| system.cpu1.dcache.WriteReq_hits 702800 # number of WriteReq hits |
| system.cpu1.dcache.WriteReq_miss_rate 0.041599 # miss rate for WriteReq accesses |
| system.cpu1.dcache.WriteReq_misses 30505 # number of WriteReq misses |
| system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. |
| system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses |
| system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency |
| system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu1.dcache.demand_hits 1812115 # number of demand (read+write) hits |
| system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles |
| system.cpu1.dcache.demand_miss_rate 0.038293 # miss rate for demand accesses |
| system.cpu1.dcache.demand_misses 72155 # number of demand (read+write) misses |
| system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles |
| system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses |
| system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses |
| system.cpu1.dcache.fast_writes 0 # number of fast writes performed |
| system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses |
| system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency |
| system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu1.dcache.overall_hits 1812115 # number of overall hits |
| system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles |
| system.cpu1.dcache.overall_miss_rate 0.038293 # miss rate for overall accesses |
| system.cpu1.dcache.overall_misses 72155 # number of overall misses |
| system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits |
| system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles |
| system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses |
| system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses |
| system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu1.dcache.replacements 62341 # number of replacements |
| system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. |
| system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use |
| system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. |
| system.cpu1.dcache.warmup_cycle 1851266680500 # Cycle when the warmup percentage was hit. |
| system.cpu1.dcache.writebacks 30850 # number of writebacks |
| system.cpu1.dtb.accesses 323622 # DTB accesses |
| system.cpu1.dtb.acv 116 # DTB access violations |
| system.cpu1.dtb.hits 1914885 # DTB hits |
| system.cpu1.dtb.misses 3692 # DTB misses |
| system.cpu1.dtb.read_accesses 220342 # DTB read accesses |
| system.cpu1.dtb.read_acv 58 # DTB read access violations |
| system.cpu1.dtb.read_hits 1163439 # DTB read hits |
| system.cpu1.dtb.read_misses 3277 # DTB read misses |
| system.cpu1.dtb.write_accesses 103280 # DTB write accesses |
| system.cpu1.dtb.write_acv 58 # DTB write access violations |
| system.cpu1.dtb.write_hits 751446 # DTB write hits |
| system.cpu1.dtb.write_misses 415 # DTB write misses |
| system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) |
| system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits |
| system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses |
| system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses |
| system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. |
| system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses |
| system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency |
| system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits |
| system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles |
| system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses |
| system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses |
| system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles |
| system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses |
| system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses |
| system.cpu1.icache.fast_writes 0 # number of fast writes performed |
| system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses |
| system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency |
| system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu1.icache.overall_hits 5832135 # number of overall hits |
| system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles |
| system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses |
| system.cpu1.icache.overall_misses 103636 # number of overall misses |
| system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits |
| system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles |
| system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses |
| system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses |
| system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu1.icache.replacements 103097 # number of replacements |
| system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. |
| system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu1.icache.tagsinuse 427.126316 # Cycle average of tags in use |
| system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. |
| system.cpu1.icache.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. |
| system.cpu1.icache.writebacks 0 # number of writebacks |
| system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles |
| system.cpu1.itb.accesses 1469938 # ITB accesses |
| system.cpu1.itb.acv 57 # ITB acv |
| system.cpu1.itb.hits 1468399 # ITB hits |
| system.cpu1.itb.misses 1539 # ITB misses |
| system.cpu1.kern.callpal 32131 # number of callpals executed |
| system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed |
| system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed |
| system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed |
| system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed |
| system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed |
| system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed |
| system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed |
| system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed |
| system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed |
| system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed |
| system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed |
| system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed |
| system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed |
| system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed |
| system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed |
| system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed |
| system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed |
| system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed |
| system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed |
| system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl |
| system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl |
| system.cpu1.kern.ipl_ticks 1870124056000 # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks_0 1859122637500 99.41% 99.41% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl |
| system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl |
| system.cpu1.kern.mode_good_kernel 612 |
| system.cpu1.kern.mode_good_user 580 |
| system.cpu1.kern.mode_good_idle 32 |
| system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches |
| system.cpu1.kern.mode_switch_user 580 # number of protection mode switches |
| system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches |
| system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches |
| system.cpu1.kern.mode_ticks_kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode |
| system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode |
| system.cpu1.kern.mode_ticks_idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode |
| system.cpu1.kern.swap_context 471 # number of times the context was actually changed |
| system.cpu1.kern.syscall 100 # number of syscalls executed |
| system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed |
| system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed |
| system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed |
| system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed |
| system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed |
| system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed |
| system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed |
| system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed |
| system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed |
| system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed |
| system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed |
| system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed |
| system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed |
| system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed |
| system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed |
| system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed |
| system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed |
| system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles |
| system.cpu1.numCycles 3740248139 # number of cpu cycles simulated |
| system.cpu1.num_insts 5931963 # Number of instructions executed |
| system.cpu1.num_refs 1926645 # Number of memory references |
| system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). |
| system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). |
| system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. |
| system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. |
| system.disk0.dma_write_txs 395 # Number of DMA write transactions. |
| system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). |
| system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). |
| system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. |
| system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. |
| system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) |
| system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses |
| system.iocache.ReadReq_misses 175 # number of ReadReq misses |
| system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) |
| system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses |
| system.iocache.WriteReq_misses 41552 # number of WriteReq misses |
| system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.iocache.blocked_no_targets 0 # number of cycles access was blocked |
| system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.iocache.cache_copies 0 # number of cache copies performed |
| system.iocache.demand_accesses 41727 # number of demand (read+write) accesses |
| system.iocache.demand_avg_miss_latency 0 # average overall miss latency |
| system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.iocache.demand_hits 0 # number of demand (read+write) hits |
| system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles |
| system.iocache.demand_miss_rate 1 # miss rate for demand accesses |
| system.iocache.demand_misses 41727 # number of demand (read+write) misses |
| system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles |
| system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses |
| system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses |
| system.iocache.fast_writes 0 # number of fast writes performed |
| system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.iocache.overall_accesses 41727 # number of overall (read+write) accesses |
| system.iocache.overall_avg_miss_latency 0 # average overall miss latency |
| system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.iocache.overall_hits 0 # number of overall hits |
| system.iocache.overall_miss_latency 0 # number of overall miss cycles |
| system.iocache.overall_miss_rate 1 # miss rate for overall accesses |
| system.iocache.overall_misses 41727 # number of overall misses |
| system.iocache.overall_mshr_hits 0 # number of overall MSHR hits |
| system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles |
| system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses |
| system.iocache.overall_mshr_misses 0 # number of overall MSHR misses |
| system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.iocache.replacements 41695 # number of replacements |
| system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. |
| system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.iocache.tagsinuse 0.435434 # Cycle average of tags in use |
| system.iocache.total_refs 0 # Total number of references to valid blocks. |
| system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. |
| system.iocache.writebacks 41520 # number of writebacks |
| system.l2c.ReadExReq_accesses 306246 # number of ReadExReq accesses(hits+misses) |
| system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses |
| system.l2c.ReadExReq_misses 306246 # number of ReadExReq misses |
| system.l2c.ReadReq_accesses 2724148 # number of ReadReq accesses(hits+misses) |
| system.l2c.ReadReq_hits 1759614 # number of ReadReq hits |
| system.l2c.ReadReq_miss_rate 0.354068 # miss rate for ReadReq accesses |
| system.l2c.ReadReq_misses 964534 # number of ReadReq misses |
| system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) |
| system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses |
| system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses |
| system.l2c.Writeback_accesses 427643 # number of Writeback accesses(hits+misses) |
| system.l2c.Writeback_hits 427643 # number of Writeback hits |
| system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.l2c.avg_refs 1.789371 # Average number of references to valid blocks. |
| system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.l2c.blocked_no_targets 0 # number of cycles access was blocked |
| system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.l2c.cache_copies 0 # number of cache copies performed |
| system.l2c.demand_accesses 3030394 # number of demand (read+write) accesses |
| system.l2c.demand_avg_miss_latency 0 # average overall miss latency |
| system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.l2c.demand_hits 1759614 # number of demand (read+write) hits |
| system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles |
| system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses |
| system.l2c.demand_misses 1270780 # number of demand (read+write) misses |
| system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles |
| system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses |
| system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses |
| system.l2c.fast_writes 0 # number of fast writes performed |
| system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.l2c.overall_accesses 3030394 # number of overall (read+write) accesses |
| system.l2c.overall_avg_miss_latency 0 # average overall miss latency |
| system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency |
| system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.l2c.overall_hits 1759614 # number of overall hits |
| system.l2c.overall_miss_latency 0 # number of overall miss cycles |
| system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses |
| system.l2c.overall_misses 1270780 # number of overall misses |
| system.l2c.overall_mshr_hits 0 # number of overall MSHR hits |
| system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles |
| system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses |
| system.l2c.overall_mshr_misses 0 # number of overall MSHR misses |
| system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.l2c.replacements 1056801 # number of replacements |
| system.l2c.sampled_refs 1091450 # Sample count of references to valid blocks. |
| system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.l2c.tagsinuse 30522.435313 # Cycle average of tags in use |
| system.l2c.total_refs 1953009 # Total number of references to valid blocks. |
| system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. |
| system.l2c.writebacks 123879 # number of writebacks |
| system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post |
| system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post |
| system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post |
| system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post |
| system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post |
| system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post |
| system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post |
| system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post |
| system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post |
| system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA |
| system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |
| system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |
| system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA |
| system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU |
| system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR |
| system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR |
| system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR |
| system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR |
| system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR |
| system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR |
| system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR |
| |
| ---------- End Simulation Statistics ---------- |
