| [root] | |
| type=Root | |
| children=system | |
| dummy=0 | |
| [system] | |
| type=System | |
| children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus | |
| mem_mode=timing | |
| physmem=system.physmem | |
| [system.cpu0] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[0] | |
| test=system.cpu0.l1c.cpu_side | |
| [system.cpu0.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu0.test | |
| mem_side=system.toL2Bus.port[1] | |
| [system.cpu1] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[1] | |
| test=system.cpu1.l1c.cpu_side | |
| [system.cpu1.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu1.test | |
| mem_side=system.toL2Bus.port[2] | |
| [system.cpu2] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[2] | |
| test=system.cpu2.l1c.cpu_side | |
| [system.cpu2.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu2.test | |
| mem_side=system.toL2Bus.port[3] | |
| [system.cpu3] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[3] | |
| test=system.cpu3.l1c.cpu_side | |
| [system.cpu3.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu3.test | |
| mem_side=system.toL2Bus.port[4] | |
| [system.cpu4] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[4] | |
| test=system.cpu4.l1c.cpu_side | |
| [system.cpu4.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu4.test | |
| mem_side=system.toL2Bus.port[5] | |
| [system.cpu5] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[5] | |
| test=system.cpu5.l1c.cpu_side | |
| [system.cpu5.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu5.test | |
| mem_side=system.toL2Bus.port[6] | |
| [system.cpu6] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[6] | |
| test=system.cpu6.l1c.cpu_side | |
| [system.cpu6.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu6.test | |
| mem_side=system.toL2Bus.port[7] | |
| [system.cpu7] | |
| type=MemTest | |
| children=l1c | |
| atomic=false | |
| max_loads=100000 | |
| memory_size=65536 | |
| percent_dest_unaligned=50 | |
| percent_functional=50 | |
| percent_reads=65 | |
| percent_source_unaligned=50 | |
| percent_uncacheable=10 | |
| progress_interval=10000 | |
| trace_addr=0 | |
| functional=system.funcmem.port[7] | |
| test=system.cpu7.l1c.cpu_side | |
| [system.cpu7.l1c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=4 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=1000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=12 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=10000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=32768 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=8 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.cpu7.test | |
| mem_side=system.toL2Bus.port[8] | |
| [system.funcmem] | |
| type=PhysicalMemory | |
| file= | |
| latency=1 | |
| range=0:134217727 | |
| zero=false | |
| port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional | |
| [system.l2c] | |
| type=BaseCache | |
| addr_range=0:18446744073709551615 | |
| assoc=8 | |
| block_size=64 | |
| cpu_side_filter_ranges= | |
| hash_delay=1 | |
| latency=10000 | |
| lifo=false | |
| max_miss_count=0 | |
| mem_side_filter_ranges= | |
| mshrs=92 | |
| prefetch_access=false | |
| prefetch_cache_check_push=true | |
| prefetch_data_accesses_only=false | |
| prefetch_degree=1 | |
| prefetch_latency=100000 | |
| prefetch_miss=false | |
| prefetch_past_page=false | |
| prefetch_policy=none | |
| prefetch_serial_squash=false | |
| prefetch_use_cpu_id=true | |
| prefetcher_size=100 | |
| prioritizeRequests=false | |
| repl=Null | |
| size=65536 | |
| split=false | |
| split_size=0 | |
| subblock_size=0 | |
| tgts_per_mshr=16 | |
| trace_addr=0 | |
| two_queue=false | |
| write_buffers=8 | |
| cpu_side=system.toL2Bus.port[0] | |
| mem_side=system.membus.port[0] | |
| [system.membus] | |
| type=Bus | |
| block_size=64 | |
| bus_id=0 | |
| clock=2 | |
| header_cycles=1 | |
| responder_set=false | |
| width=16 | |
| port=system.l2c.mem_side system.physmem.port[0] | |
| [system.physmem] | |
| type=PhysicalMemory | |
| file= | |
| latency=1 | |
| range=0:134217727 | |
| zero=false | |
| port=system.membus.port[1] | |
| [system.toL2Bus] | |
| type=Bus | |
| block_size=64 | |
| bus_id=0 | |
| clock=2 | |
| header_cycles=1 | |
| responder_set=false | |
| width=16 | |
| port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side | |