commit d1251cd2c64a6bdbca38b65a7a9dc533c54f7f5c
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Aug 30 14:31:57 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 19:59:58 2019 +0000
tree bdaa64bbb604f97679329476ecd974f984832d9c
parent 665b67e365b11e791ff23b833d866d9ca4ffee77

arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex

Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/insts/mem64.hh

diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 4fbbe77..886c54f 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -49,13 +49,13 @@
 {
   protected:
     IntRegIndex base;
-    IntRegIndex dest;
+    MiscRegIndex dest;
     uint64_t imm;
 
     SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-            IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm)
+            IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
         : MiscRegOp64(mnem, _machInst, __opClass, false),
-          base(_base), dest((IntRegIndex)miscReg), imm(_imm)
+          base(_base), dest(_dest), imm(_imm)
     {}
 
     std::string generateDisassembly(