commit d64465c02482fc2afa4c1467650976856c9a440a
author Gabe Black <gabeblack@google.com> Sun Aug 30 01:32:43 2020 -0700
committer Gabe Black <gabeblack@google.com> Tue Sep 15 08:03:19 2020 +0000
tree 1827acc02a6ae7d983b4c069a34bb791d4616b8a
parent 340a16ac1c5731d4def3bfea98b9ed0e53b92d57

mips,cpu: Get rid of the IsERET StaticInst flag.

This is set by MIPS but doesn't have an accessor in StaticInst, and
isn't used by anything.

Change-Id: Ie28d2df134dcf264bca17c9c66dd32515a240492
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33738
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/arch/mips/isa/decoder.isa

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index f62000e..76453b0 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -719,7 +719,7 @@
                         LLFlag = 0;
                         Status = status;
                         SRSCtl = srsCtl;
-                    }}, IsReturn, IsSerializing, IsERET);
+                    }}, IsReturn, IsSerializing);
 
                     0x1F: deret({{
                         DebugReg debug = Debug;
@@ -732,7 +732,7 @@
                             // Undefined;
                         }
                         Debug = debug;
-                    }}, IsReturn, IsSerializing, IsERET);
+                    }}, IsReturn, IsSerializing);
                 }
                 format CP0TLB {
                     0x01: tlbr({{

src/cpu/StaticInstFlags.py

diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index acaa7bf..b70f919 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -85,7 +85,6 @@
         'IsMemBarrier',     # Is a memory barrier
         'IsWriteBarrier',   # Is a write barrier
         'IsReadBarrier',    # Is a read barrier
-        'IsERET',           # <- Causes the IFU to stall (MIPS ISA)
 
         'IsNonSpeculative', # Should not be executed speculatively
         'IsQuiesce',        # Is a quiesce instruction