commit d8224e5c7e08d536017f64a32a053053ebda44a3
author Gabe Black <gabe.black@gmail.com> Mon Nov 01 23:22:57 2021 -0700
committer Gabe Black <gabe.black@gmail.com> Tue Aug 02 06:01:42 2022 -0700
tree 15c3390c995954a28ec921eeab5312d33375f61e
parent 890535d0152cdf3d21616b7da15ef497a621fc40

arch-x86,cpu: Override the int div latency local to x86.

Remove the ISA check when selecting the default integer division latency
for O3. Instead, create a parameter which the latency defaults to using
a proxy, and then override that parameter when setting the default
function unit pool in the x86 version of that CPU. The value can still
be overridden if the user wants, but this way it gets its specialized
value within x86 with no ISA check.

Change-Id: I1ef9ee94f4b16aebe03e043df5cdc6167efe6e64

src/arch/x86/X86CPU.py

diff --git a/src/arch/x86/X86CPU.py b/src/arch/x86/X86CPU.py
index 0b46c94..f5653c1 100644
--- a/src/arch/x86/X86CPU.py
+++ b/src/arch/x86/X86CPU.py
@@ -29,6 +29,7 @@
 from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
 from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
 from m5.objects.BaseO3CPU import BaseO3CPU
+from m5.objects.FUPool import DefaultFUPool
 from m5.objects.X86Decoder import X86Decoder
 from m5.objects.X86MMU import X86MMU
 from m5.objects.X86LocalApic import X86LocalApic
@@ -60,3 +61,9 @@
     # (it's a side effect of int reg renaming), so they should
     # never be the bottleneck here.
     numPhysCCRegs = Self.numPhysIntRegs * 5
+
+    # DIV and IDIV instructions in x86 are implemented using a loop which
+    # issues division microops.  The latency of these microops should really be
+    # one (or a small number) cycle each since each of these computes one bit
+    # of the quotient.
+    fuPool = DefaultFUPool(int_div_lat=1)

src/cpu/o3/FUPool.py

diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index e9d606e..6d48ce7 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -47,6 +47,10 @@
     cxx_header = "cpu/o3/fu_pool.hh"
     FUList = VectorParam.FUDesc("list of FU's for this pool")
 
+    # This latency may need to be specialized for x86. This makes it easy to
+    # access in subclasses.
+    int_div_lat = Param.Cycles(20, "Default latency for IntDiv")
+
 class DefaultFUPool(FUPool):
     FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
                SIMD_Unit(), PredALU(), WritePort(), RdWrPort(), IprPort() ]

src/cpu/o3/FuncUnitConfig.py

diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index c5e2898..50cb42b 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -39,6 +39,7 @@
 from m5.SimObject import SimObject
 from m5.defines import buildEnv
 from m5.params import *
+from m5.proxy import *
 
 from m5.objects.FuncUnit import *
 
@@ -48,14 +49,8 @@
 
 class IntMultDiv(FUDesc):
     opList = [ OpDesc(opClass='IntMult', opLat=3),
-               OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
-
-    # DIV and IDIV instructions in x86 are implemented using a loop which
-    # issues division microops.  The latency of these microops should really be
-    # one (or a small number) cycle each since each of these computes one bit
-    # of the quotient.
-    if buildEnv['USE_X86_ISA']:
-        opList[1].opLat=1
+               OpDesc(opClass='IntDiv', opLat=Parent.int_div_lat,
+                   pipelined=False) ]
 
     count=2