| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000247 |
| sim_ticks 246972500 |
| final_tick 246972500 |
| sim_freq 1000000000000 |
| host_inst_rate 6087 |
| host_op_rate 6099 |
| host_tick_rate 13984193 |
| host_mem_usage 268924 |
| host_seconds 17.66 |
| sim_insts 107505 |
| sim_ops 107717 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.physmem.bytes_read::cpu.inst 43968 |
| system.physmem.bytes_read::cpu.data 29184 |
| system.physmem.bytes_read::total 73152 |
| system.physmem.bytes_inst_read::cpu.inst 43968 |
| system.physmem.bytes_inst_read::total 43968 |
| system.physmem.num_reads::cpu.inst 687 |
| system.physmem.num_reads::cpu.data 456 |
| system.physmem.num_reads::total 1143 |
| system.physmem.bw_read::cpu.inst 178027918 |
| system.physmem.bw_read::cpu.data 118167002 |
| system.physmem.bw_read::total 296194920 |
| system.physmem.bw_inst_read::cpu.inst 178027918 |
| system.physmem.bw_inst_read::total 178027918 |
| system.physmem.bw_total::cpu.inst 178027918 |
| system.physmem.bw_total::cpu.data 118167002 |
| system.physmem.bw_total::total 296194920 |
| system.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 45 |
| system.cpu.pwrStateResidencyTicks::ON 246972500 |
| system.cpu.numCycles 493945 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 107505 |
| system.cpu.committedOps 107717 |
| system.cpu.num_int_alu_accesses 107132 |
| system.cpu.num_fp_alu_accesses 12 |
| system.cpu.num_vec_alu_accesses 0 |
| system.cpu.num_func_calls 6215 |
| system.cpu.num_conditional_control_insts 17634 |
| system.cpu.num_int_insts 107132 |
| system.cpu.num_fp_insts 12 |
| system.cpu.num_vec_insts 0 |
| system.cpu.num_int_register_reads 134283 |
| system.cpu.num_int_register_writes 70918 |
| system.cpu.num_fp_register_reads 12 |
| system.cpu.num_fp_register_writes 0 |
| system.cpu.num_vec_register_reads 0 |
| system.cpu.num_vec_register_writes 0 |
| system.cpu.num_mem_refs 41605 |
| system.cpu.num_load_insts 25266 |
| system.cpu.num_store_insts 16339 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 493945 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 23849 |
| system.cpu.op_class::No_OpClass 49 0.05% 0.05% |
| system.cpu.op_class::IntAlu 65954 61.20% 61.25% |
| system.cpu.op_class::IntMult 124 0.12% 61.36% |
| system.cpu.op_class::IntDiv 30 0.03% 61.39% |
| system.cpu.op_class::FloatAdd 0 0.00% 61.39% |
| system.cpu.op_class::FloatCmp 0 0.00% 61.39% |
| system.cpu.op_class::FloatCvt 0 0.00% 61.39% |
| system.cpu.op_class::FloatMult 0 0.00% 61.39% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 61.39% |
| system.cpu.op_class::FloatDiv 0 0.00% 61.39% |
| system.cpu.op_class::FloatMisc 0 0.00% 61.39% |
| system.cpu.op_class::FloatSqrt 0 0.00% 61.39% |
| system.cpu.op_class::SimdAdd 0 0.00% 61.39% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 61.39% |
| system.cpu.op_class::SimdAlu 0 0.00% 61.39% |
| system.cpu.op_class::SimdCmp 0 0.00% 61.39% |
| system.cpu.op_class::SimdCvt 0 0.00% 61.39% |
| system.cpu.op_class::SimdMisc 0 0.00% 61.39% |
| system.cpu.op_class::SimdMult 0 0.00% 61.39% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 61.39% |
| system.cpu.op_class::SimdShift 0 0.00% 61.39% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 61.39% |
| system.cpu.op_class::SimdSqrt 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatMisc 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.39% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.39% |
| system.cpu.op_class::MemRead 25266 23.45% 84.84% |
| system.cpu.op_class::MemWrite 16327 15.15% 99.99% |
| system.cpu.op_class::FloatMemRead 0 0.00% 99.99% |
| system.cpu.op_class::FloatMemWrite 12 0.01% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 107762 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu.dcache.tags.replacements 0 |
| system.cpu.dcache.tags.tagsinuse 327.838970 |
| system.cpu.dcache.tags.total_refs 41149 |
| system.cpu.dcache.tags.sampled_refs 456 |
| system.cpu.dcache.tags.avg_refs 90.239035 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 327.838970 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.080039 |
| system.cpu.dcache.tags.occ_percent::total 0.080039 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 456 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 11 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 432 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.111328 |
| system.cpu.dcache.tags.tag_accesses 83666 |
| system.cpu.dcache.tags.data_accesses 83666 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 24798 |
| system.cpu.dcache.ReadReq_hits::total 24798 |
| system.cpu.dcache.WriteReq_hits::cpu.data 15879 |
| system.cpu.dcache.WriteReq_hits::total 15879 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 235 |
| system.cpu.dcache.LoadLockedReq_hits::total 235 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 237 |
| system.cpu.dcache.StoreCondReq_hits::total 237 |
| system.cpu.dcache.demand_hits::cpu.data 40677 |
| system.cpu.dcache.demand_hits::total 40677 |
| system.cpu.dcache.overall_hits::cpu.data 40677 |
| system.cpu.dcache.overall_hits::total 40677 |
| system.cpu.dcache.ReadReq_misses::cpu.data 231 |
| system.cpu.dcache.ReadReq_misses::total 231 |
| system.cpu.dcache.WriteReq_misses::cpu.data 223 |
| system.cpu.dcache.WriteReq_misses::total 223 |
| system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 |
| system.cpu.dcache.LoadLockedReq_misses::total 2 |
| system.cpu.dcache.demand_misses::cpu.data 454 |
| system.cpu.dcache.demand_misses::total 454 |
| system.cpu.dcache.overall_misses::cpu.data 454 |
| system.cpu.dcache.overall_misses::total 454 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 14553000 |
| system.cpu.dcache.ReadReq_miss_latency::total 14553000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 14049000 |
| system.cpu.dcache.WriteReq_miss_latency::total 14049000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 |
| system.cpu.dcache.demand_miss_latency::cpu.data 28602000 |
| system.cpu.dcache.demand_miss_latency::total 28602000 |
| system.cpu.dcache.overall_miss_latency::cpu.data 28602000 |
| system.cpu.dcache.overall_miss_latency::total 28602000 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 25029 |
| system.cpu.dcache.ReadReq_accesses::total 25029 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 16102 |
| system.cpu.dcache.WriteReq_accesses::total 16102 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 237 |
| system.cpu.dcache.LoadLockedReq_accesses::total 237 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 237 |
| system.cpu.dcache.StoreCondReq_accesses::total 237 |
| system.cpu.dcache.demand_accesses::cpu.data 41131 |
| system.cpu.dcache.demand_accesses::total 41131 |
| system.cpu.dcache.overall_accesses::cpu.data 41131 |
| system.cpu.dcache.overall_accesses::total 41131 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009229 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.009229 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013849 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.013849 |
| system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.008439 |
| system.cpu.dcache.LoadLockedReq_miss_rate::total 0.008439 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.011038 |
| system.cpu.dcache.demand_miss_rate::total 0.011038 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.011038 |
| system.cpu.dcache.overall_miss_rate::total 0.011038 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.demand_avg_miss_latency::total 63000 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.overall_avg_miss_latency::total 63000 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 231 |
| system.cpu.dcache.ReadReq_mshr_misses::total 231 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 223 |
| system.cpu.dcache.WriteReq_mshr_misses::total 223 |
| system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2 |
| system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 454 |
| system.cpu.dcache.demand_mshr_misses::total 454 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 454 |
| system.cpu.dcache.overall_mshr_misses::total 454 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14322000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 14322000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13826000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 13826000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 124000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 124000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28148000 |
| system.cpu.dcache.demand_mshr_miss_latency::total 28148000 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28148000 |
| system.cpu.dcache.overall_mshr_miss_latency::total 28148000 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.009229 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.009229 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013849 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013849 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.008439 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.008439 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.011038 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.011038 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011038 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.011038 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu.icache.tags.replacements 34 |
| system.cpu.icache.tags.tagsinuse 404.619001 |
| system.cpu.icache.tags.total_refs 133800 |
| system.cpu.icache.tags.sampled_refs 688 |
| system.cpu.icache.tags.avg_refs 194.476744 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 404.619001 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.197568 |
| system.cpu.icache.tags.occ_percent::total 0.197568 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 654 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 42 |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 111 |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 501 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.319336 |
| system.cpu.icache.tags.tag_accesses 269664 |
| system.cpu.icache.tags.data_accesses 269664 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu.icache.ReadReq_hits::cpu.inst 133800 |
| system.cpu.icache.ReadReq_hits::total 133800 |
| system.cpu.icache.demand_hits::cpu.inst 133800 |
| system.cpu.icache.demand_hits::total 133800 |
| system.cpu.icache.overall_hits::cpu.inst 133800 |
| system.cpu.icache.overall_hits::total 133800 |
| system.cpu.icache.ReadReq_misses::cpu.inst 688 |
| system.cpu.icache.ReadReq_misses::total 688 |
| system.cpu.icache.demand_misses::cpu.inst 688 |
| system.cpu.icache.demand_misses::total 688 |
| system.cpu.icache.overall_misses::cpu.inst 688 |
| system.cpu.icache.overall_misses::total 688 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 43296500 |
| system.cpu.icache.ReadReq_miss_latency::total 43296500 |
| system.cpu.icache.demand_miss_latency::cpu.inst 43296500 |
| system.cpu.icache.demand_miss_latency::total 43296500 |
| system.cpu.icache.overall_miss_latency::cpu.inst 43296500 |
| system.cpu.icache.overall_miss_latency::total 43296500 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 134488 |
| system.cpu.icache.ReadReq_accesses::total 134488 |
| system.cpu.icache.demand_accesses::cpu.inst 134488 |
| system.cpu.icache.demand_accesses::total 134488 |
| system.cpu.icache.overall_accesses::cpu.inst 134488 |
| system.cpu.icache.overall_accesses::total 134488 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005116 |
| system.cpu.icache.ReadReq_miss_rate::total 0.005116 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.005116 |
| system.cpu.icache.demand_miss_rate::total 0.005116 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.005116 |
| system.cpu.icache.overall_miss_rate::total 0.005116 |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62930.959302 |
| system.cpu.icache.ReadReq_avg_miss_latency::total 62930.959302 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 62930.959302 |
| system.cpu.icache.demand_avg_miss_latency::total 62930.959302 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 62930.959302 |
| system.cpu.icache.overall_avg_miss_latency::total 62930.959302 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.writebacks::writebacks 34 |
| system.cpu.icache.writebacks::total 34 |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 688 |
| system.cpu.icache.ReadReq_mshr_misses::total 688 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 688 |
| system.cpu.icache.demand_mshr_misses::total 688 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 688 |
| system.cpu.icache.overall_mshr_misses::total 688 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42608500 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 42608500 |
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| system.cpu.icache.demand_mshr_miss_latency::total 42608500 |
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| system.cpu.icache.overall_mshr_miss_latency::total 42608500 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005116 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005116 |
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| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 748.536096 |
| system.cpu.l2cache.tags.total_refs 35 |
| system.cpu.l2cache.tags.sampled_refs 1143 |
| system.cpu.l2cache.tags.avg_refs 0.030621 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 420.677738 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 327.858357 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.012838 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.010005 |
| system.cpu.l2cache.tags.occ_percent::total 0.022844 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 1143 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.034882 |
| system.cpu.l2cache.tags.tag_accesses 10567 |
| system.cpu.l2cache.tags.data_accesses 10567 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu.l2cache.WritebackClean_hits::writebacks 34 |
| system.cpu.l2cache.WritebackClean_hits::total 34 |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 |
| system.cpu.l2cache.ReadCleanReq_hits::total 1 |
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| system.cpu.l2cache.demand_hits::total 1 |
| system.cpu.l2cache.overall_hits::cpu.inst 1 |
| system.cpu.l2cache.overall_hits::total 1 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 223 |
| system.cpu.l2cache.ReadExReq_misses::total 223 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 687 |
| system.cpu.l2cache.ReadCleanReq_misses::total 687 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 233 |
| system.cpu.l2cache.ReadSharedReq_misses::total 233 |
| system.cpu.l2cache.demand_misses::cpu.inst 687 |
| system.cpu.l2cache.demand_misses::cpu.data 456 |
| system.cpu.l2cache.demand_misses::total 1143 |
| system.cpu.l2cache.overall_misses::cpu.inst 687 |
| system.cpu.l2cache.overall_misses::cpu.data 456 |
| system.cpu.l2cache.overall_misses::total 1143 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13491500 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 13491500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 41565000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 41565000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14096500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 14096500 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 41565000 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 27588000 |
| system.cpu.l2cache.demand_miss_latency::total 69153000 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 41565000 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 27588000 |
| system.cpu.l2cache.overall_miss_latency::total 69153000 |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 34 |
| system.cpu.l2cache.WritebackClean_accesses::total 34 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 223 |
| system.cpu.l2cache.ReadExReq_accesses::total 223 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 688 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 688 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 233 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 233 |
| system.cpu.l2cache.demand_accesses::cpu.inst 688 |
| system.cpu.l2cache.demand_accesses::cpu.data 456 |
| system.cpu.l2cache.demand_accesses::total 1144 |
| system.cpu.l2cache.overall_accesses::cpu.inst 688 |
| system.cpu.l2cache.overall_accesses::cpu.data 456 |
| system.cpu.l2cache.overall_accesses::total 1144 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998547 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998547 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998547 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_miss_rate::total 0.999126 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998547 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_miss_rate::total 0.999126 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.183406 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.183406 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.183406 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60501.312336 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.183406 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60501.312336 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 223 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 223 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 687 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 687 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 233 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 233 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 687 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 456 |
| system.cpu.l2cache.demand_mshr_misses::total 1143 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 687 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 456 |
| system.cpu.l2cache.overall_mshr_misses::total 1143 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11261500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11261500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34695000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34695000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11766500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11766500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34695000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23028000 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 57723000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34695000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23028000 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 57723000 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998547 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998547 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998547 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.999126 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998547 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.999126 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.183406 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.183406 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.183406 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.312336 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.183406 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.312336 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 1178 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 34 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 921 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 34 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 223 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 223 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 688 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 233 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1410 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 912 |
| system.cpu.toL2Bus.pkt_count::total 2322 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46208 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29184 |
| system.cpu.toL2Bus.pkt_size::total 75392 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 1144 |
| system.cpu.toL2Bus.snoop_fanout::mean 0 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 1144 100.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 0 |
| system.cpu.toL2Bus.snoop_fanout::total 1144 |
| system.cpu.toL2Bus.reqLayer0.occupancy 623000 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.3 |
| system.cpu.toL2Bus.respLayer0.occupancy 1032000 |
| system.cpu.toL2Bus.respLayer0.utilization 0.4 |
| system.cpu.toL2Bus.respLayer1.occupancy 684000 |
| system.cpu.toL2Bus.respLayer1.utilization 0.3 |
| system.membus.snoop_filter.tot_requests 1143 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 246972500 |
| system.membus.trans_dist::ReadResp 920 |
| system.membus.trans_dist::ReadExReq 223 |
| system.membus.trans_dist::ReadExResp 223 |
| system.membus.trans_dist::ReadSharedReq 920 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2286 |
| system.membus.pkt_count::total 2286 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73152 |
| system.membus.pkt_size::total 73152 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 1143 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 1143 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 1143 |
| system.membus.reqLayer0.occupancy 1144500 |
| system.membus.reqLayer0.utilization 0.5 |
| system.membus.respLayer1.occupancy 5715000 |
| system.membus.respLayer1.utilization 2.3 |
| |
| ---------- End Simulation Statistics ---------- |
