commit dc70987e470d66f584e0ddf606e9f07da994ba75
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 14:44:47 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Sep 18 13:30:01 2019 +0000
tree 4c79dd20570f9378b8835b4c52335139fd95fb79
parent 0e4c3437fdfb20e0f0d590e0d0abe32fc8393b3c

arch-arm: ISV bit in DataAbort should check for translation stage

According to the ESR spec, the ISV bit is set to 1 only for stage 2
aborts.

Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/faults.cc

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ba51519..c5858c9 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1371,7 +1371,7 @@
     val  = AbortFault<DataAbort>::iss();
     // ISS is valid if not caused by a stage 1 page table walk, and when taken
     // to AArch64 only when directed to EL2
-    if (!s1ptw && (!to64 || toEL == EL2)) {
+    if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
         val |= isv << 24;
         if (isv) {
             val |= sas << 22;