src/arch/riscv/isa_traits.hh

/*
 * Copyright (c) 2013 ARM Limited
 * Copyright (c) 2014-2015 Sven Karlsson
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
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 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2016 The University of Virginia
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#ifndef __ARCH_RISCV_ISA_TRAITS_HH__
#define __ARCH_RISCV_ISA_TRAITS_HH__

#include "base/types.hh"
#include "sim/byteswap.hh"

namespace RiscvISA
{

const ByteOrder GuestByteOrder = ByteOrder::little;

const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;

}

#endif //__ARCH_RISCV_ISA_TRAITS_HH__