arch-arm: don't expose FEAT_VHE by default
If FEAT_VHE is implemented and Linux boots in EL2, it programs itself
to operate in EL2. This causes a later boot stall as explained in
https://gem5.atlassian.net/browse/GEM5-901.
We provide a parameter "have_vhe" to enable FEAT_VHE on demand. This is
disabled by default until fixed. This avoids users stalling on the common
case of booting Linux without a hypervisor.
Change-Id: I3ee7be1ca59afc0cbbda59fb3aad4c897c06405f
Signed-off-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39695
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index ebad774..0725726 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2020 ARM Limited
+# Copyright (c) 2012-2013, 2015-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -108,8 +108,8 @@
# 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
"AArch64 Memory Model Feature Register 0")
- # PAN | HPDS | VHE
- id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101100,
+ # PAN | HPDS | !VHE
+ id_aa64mmfr1_el1 = Param.UInt64(0x0000000000101000,
"AArch64 Memory Model Feature Register 1")
id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Memory Model Feature Register 2")
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 0ca782f..b2e58a3 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
+# Copyright (c) 2009, 2012-2013, 2015-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -73,6 +73,8 @@
"SVE vector length in quadwords (128-bit)")
have_lse = Param.Bool(True,
"True if LSE is implemented (ARMv8.1)")
+ have_vhe = Param.Bool(False,
+ "True if FEAT_VHE (Virtualization Host Extensions) is implemented")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
have_secel2 = Param.Bool(True,
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 4ad1125..8adbdab 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -88,6 +88,7 @@
haveLargeAsid64 = system->haveLargeAsid64();
physAddrRange = system->physAddrRange();
haveSVE = system->haveSVE();
+ haveVHE = system->haveVHE();
havePAN = system->havePAN();
haveSecEL2 = system->haveSecEL2();
sveVL = system->sveVL();
@@ -100,6 +101,7 @@
haveLargeAsid64 = false;
physAddrRange = 32; // dummy value
haveSVE = true;
+ haveVHE = false;
havePAN = false;
haveSecEL2 = true;
sveVL = p->sve_vl_se;
@@ -425,6 +427,10 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
haveLSE ? 0x2 : 0x0);
+ // VHE
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
+ miscRegs[MISCREG_ID_AA64MMFR1_EL1], 11, 8,
+ haveVHE ? 0x1 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 910dc2c..40fa561 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -94,6 +94,7 @@
uint8_t physAddrRange;
bool haveSVE;
bool haveLSE;
+ bool haveVHE;
bool havePAN;
bool haveSecEL2;
bool haveTME;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 7009b31..0bbc701 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -71,12 +71,13 @@
_haveSVE(p->have_sve),
_sveVL(p->sve_vl),
_haveLSE(p->have_lse),
+ _haveVHE(p->have_vhe),
_havePAN(p->have_pan),
_haveSecEL2(p->have_secel2),
semihosting(p->semihosting),
multiProc(p->multi_proc)
{
- if (p->auto_reset_addr) {
+ if (p->auto_reset_addr) {
_resetAddr = workload->getEntry();
} else {
_resetAddr = p->reset_addr;
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 62dfe76..eb4da94 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013, 2015-2020 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -130,6 +130,9 @@
*/
const bool _haveLSE;
+ /** True if FEAT_VHE (Virtualization Host Extensions) is implemented */
+ const bool _haveVHE;
+
/** True if Priviledge Access Never is implemented */
const unsigned _havePAN;
@@ -236,6 +239,9 @@
/** Returns true if LSE is implemented (ARMv8.1) */
bool haveLSE() const { return _haveLSE; }
+ /** Returns true if Virtualization Host Extensions is implemented */
+ bool haveVHE() const { return _haveVHE; }
+
/** Returns true if Priviledge Access Never is implemented */
bool havePAN() const { return _havePAN; }
