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# Copyright 2019 Google, Inc.
#
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from m5.params import *
from m5.proxy import *
from m5.objects.BaseCPU import BaseCPU
from m5.objects.BaseTLB import BaseTLB
class IrisTLB(BaseTLB):
type = 'IrisTLB'
cxx_class = 'Iris::TLB'
cxx_header = 'arch/arm/fastmodel/iris/tlb.hh'
class IrisBaseCPU(BaseCPU):
type = 'IrisBaseCPU'
abstract = True
cxx_class = 'Iris::BaseCPU'
cxx_header = 'arch/arm/fastmodel/iris/cpu.hh'
@classmethod
def memory_mode(cls):
return 'atomic_noncaching'
@classmethod
def require_caches(cls):
return False
@classmethod
def support_take_over(cls):
#TODO Make this work.
return False
evs = Param.SystemC_ScModule(
"Fast model exported virtual subsystem holding cores")
thread_paths = VectorParam.String(
"Sub-paths to elements in the EVS which support a thread context")
dtb = IrisTLB()
itb = IrisTLB()