src/arch/riscv/fs_workload.hh

/*
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2007 MIPS Technologies, Inc.
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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 * documentation and/or other materials provided with the distribution;
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __ARCH_RISCV_FS_WORKLOAD_HH__
#define __ARCH_RISCV_FS_WORKLOAD_HH__

#include "params/RiscvFsWorkload.hh"
#include "sim/sim_object.hh"
#include "sim/workload.hh"

namespace RiscvISA
{

class FsWorkload : public Workload
{
  protected:
    // checker for bare metal application
    bool _isBareMetal;
    // entry point for simulation
    Addr _resetVect;

  public:
    FsWorkload(RiscvFsWorkloadParams *p) : Workload(p),
        _isBareMetal(p->bare_metal), _resetVect(p->reset_vect)
    {}

    // return reset vector
    Addr resetVect() const { return _resetVect; }

    // return bare metal checker
    bool isBareMetal() const { return _isBareMetal; }

    Addr getEntry() const override { return _resetVect; }
};

} // namespace RiscvISA

#endif // __ARCH_RISCV_FS_WORKLOAD_HH__