| // -*- mode:c++ -*- |
| |
| // Copyright (c) 2007 MIPS Technologies, Inc. |
| // All rights reserved. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| def operand_types {{ |
| 'sb' : 'int8_t', |
| 'ub' : 'uint8_t', |
| 'sh' : 'int16_t', |
| 'uh' : 'uint16_t', |
| 'sw' : 'int32_t', |
| 'uw' : 'uint32_t', |
| 'sd' : 'int64_t', |
| 'ud' : 'uint64_t', |
| 'sf' : 'float', |
| 'df' : 'double' |
| }}; |
| |
| def operands {{ |
| #General Purpose Integer Reg Operands |
| 'Rd': IntRegOp('uw', 'RD', 'IsInteger', 1), |
| 'Rs': IntRegOp('uw', 'RS', 'IsInteger', 2), |
| 'Rt': IntRegOp('uw', 'RT', 'IsInteger', 3), |
| |
| #Immediate Value operand |
| 'IntImm': IntRegOp('uw', 'INTIMM', 'IsInteger', 3), |
| |
| #Operands used for Link Insts |
| 'R31': IntRegOp('uw', '31', 'IsInteger', 4), |
| |
| #Special Integer Reg operands |
| 'LO0': IntRegOp('uw', 'INTREG_LO', 'IsInteger', 6), |
| 'HI0': IntRegOp('uw', 'INTREG_HI', 'IsInteger', 7), |
| |
| #Bitfield-dependent HI/LO Register Access |
| 'LO_RD_SEL': IntRegOp('uw', 'INTREG_DSP_LO0 + ACDST*3', None, 6), |
| 'HI_RD_SEL': IntRegOp('uw', 'INTREG_DSP_HI0 + ACDST*3', None, 7), |
| 'LO_RS_SEL': IntRegOp('uw', 'INTREG_DSP_LO0 + ACSRC*3', None, 6), |
| 'HI_RS_SEL': IntRegOp('uw', 'INTREG_DSP_HI0 + ACSRC*3', None, 7), |
| |
| #DSP Special Purpose Integer Operands |
| 'DSPControl': IntRegOp('uw', 'INTREG_DSP_CONTROL', None, 8), |
| 'DSPLo0': IntRegOp('uw', 'INTREG_LO', None, 1), |
| 'DSPHi0': IntRegOp('uw', 'INTREG_HI', None, 1), |
| 'DSPACX0': IntRegOp('uw', 'INTREG_DSP_ACX0', None, 1), |
| 'DSPLo1': IntRegOp('uw', 'INTREG_DSP_LO1', None, 1), |
| 'DSPHi1': IntRegOp('uw', 'INTREG_DSP_HI1', None, 1), |
| 'DSPACX1': IntRegOp('uw', 'INTREG_DSP_ACX1', None, 1), |
| 'DSPLo2': IntRegOp('uw', 'INTREG_DSP_LO2', None, 1), |
| 'DSPHi2': IntRegOp('uw', 'INTREG_DSP_HI2', None, 1), |
| 'DSPACX2': IntRegOp('uw', 'INTREG_DSP_ACX2', None, 1), |
| 'DSPLo3': IntRegOp('uw', 'INTREG_DSP_LO3', None, 1), |
| 'DSPHi3': IntRegOp('uw', 'INTREG_DSP_HI3', None, 1), |
| 'DSPACX3': IntRegOp('uw', 'INTREG_DSP_ACX3', None, 1), |
| |
| #Floating Point Reg Operands |
| 'Fd': FloatRegOp('sf', 'FD', 'IsFloating', 1), |
| 'Fs': FloatRegOp('sf', 'FS', 'IsFloating', 2), |
| 'Ft': FloatRegOp('sf', 'FT', 'IsFloating', 3), |
| 'Fr': FloatRegOp('sf', 'FR', 'IsFloating', 3), |
| |
| #Special Purpose Floating Point Control Reg Operands |
| 'FIR': FloatRegOp('uw', 'FLOATREG_FIR', 'IsFloating', 1), |
| 'FCCR': FloatRegOp('uw', 'FLOATREG_FCCR', 'IsFloating', 2), |
| 'FEXR': FloatRegOp('uw', 'FLOATREG_FEXR', 'IsFloating', 3), |
| 'FENR': FloatRegOp('uw', 'FLOATREG_FENR', 'IsFloating', 3), |
| 'FCSR': FloatRegOp('uw', 'FLOATREG_FCSR', 'IsFloating', 3), |
| |
| #Operands For Paired Singles FP Operations |
| 'Fd1': FloatRegOp('sf', 'FD', 'IsFloating', 4), |
| 'Fd2': FloatRegOp('sf', 'FD+1', 'IsFloating', 4), |
| 'Fs1': FloatRegOp('sf', 'FS', 'IsFloating', 5), |
| 'Fs2': FloatRegOp('sf', 'FS+1', 'IsFloating', 5), |
| 'Ft1': FloatRegOp('sf', 'FT', 'IsFloating', 6), |
| 'Ft2': FloatRegOp('sf', 'FT+1', 'IsFloating', 6), |
| 'Fr1': FloatRegOp('sf', 'FR', 'IsFloating', 7), |
| 'Fr2': FloatRegOp('sf', 'FR+1', 'IsFloating', 7), |
| |
| #Status Control Reg |
| 'Status': ControlRegOp('uw', 'MISCREG_STATUS', None, 1), |
| |
| #LL Flag |
| 'LLFlag': ControlRegOp('uw', 'MISCREG_LLFLAG', None, 1), |
| |
| #Thread pointer value for SE mode |
| 'TpValue': ControlRegOp('ud', 'MISCREG_TP_VALUE', None, 1), |
| |
| # Index Register |
| 'Index': ControlRegOp('uw','MISCREG_INDEX',None,1), |
| |
| |
| 'CP0_RD_SEL': ControlRegOp('uw', '(RD << 3 | SEL)', None, 1), |
| |
| #MT Control Regs |
| 'MVPConf0': ControlRegOp('uw', 'MISCREG_MVP_CONF0', None, 1), |
| 'MVPControl': ControlRegOp('uw', 'MISCREG_MVP_CONTROL', None, 1), |
| 'TCBind': ControlRegOp('uw', 'MISCREG_TC_BIND', None, 1), |
| 'TCStatus': ControlRegOp('uw', 'MISCREG_TC_STATUS', None, 1), |
| 'TCRestart': ControlRegOp('uw', 'MISCREG_TC_RESTART', None, 1), |
| 'VPEConf0': ControlRegOp('uw', 'MISCREG_VPE_CONF0', None, 1), |
| 'VPEControl': ControlRegOp('uw', 'MISCREG_VPE_CONTROL', None, 1), |
| 'YQMask': ControlRegOp('uw', 'MISCREG_YQMASK', None, 1), |
| |
| #CP0 Control Regs |
| 'EntryHi': ControlRegOp('uw', 'MISCREG_ENTRYHI',None,1), |
| 'EntryLo0': ControlRegOp('uw', 'MISCREG_ENTRYLO0',None,1), |
| 'EntryLo1': ControlRegOp('uw', 'MISCREG_ENTRYLO1',None,1), |
| 'PageMask': ControlRegOp('uw', 'MISCREG_PAGEMASK',None,1), |
| 'Random': ControlRegOp('uw', 'MISCREG_CP0_RANDOM',None,1), |
| 'ErrorEPC': ControlRegOp('uw', 'MISCREG_ERROR_EPC',None,1), |
| 'EPC': ControlRegOp('uw', 'MISCREG_EPC',None,1), |
| 'DEPC': ControlRegOp('uw', 'MISCREG_DEPC',None,1), |
| 'IntCtl': ControlRegOp('uw', 'MISCREG_INTCTL',None,1), |
| 'SRSCtl': ControlRegOp('uw', 'MISCREG_SRSCTL',None,1), |
| 'Config': ControlRegOp('uw', 'MISCREG_CONFIG',None,1), |
| 'Config3': ControlRegOp('uw', 'MISCREG_CONFIG3',None,1), |
| 'Config1': ControlRegOp('uw', 'MISCREG_CONFIG1',None,1), |
| 'Config2': ControlRegOp('uw', 'MISCREG_CONFIG2',None,1), |
| 'PageGrain': ControlRegOp('uw', 'MISCREG_PAGEGRAIN',None,1), |
| 'Debug': ControlRegOp('uw', 'MISCREG_DEBUG',None,1), |
| 'Cause': ControlRegOp('uw', 'MISCREG_CAUSE',None,1), |
| |
| #Memory Operand |
| 'Mem': MemOp('uw', None, (None, 'IsLoad', 'IsStore'), 4), |
| |
| #Program Counter Operands |
| 'PC': PCStateOp('uw', 'pc', (None, None, 'IsControl'), 4), |
| 'NPC': PCStateOp('uw', 'npc', (None, None, 'IsControl'), 4), |
| 'NNPC': PCStateOp('uw', 'nnpc', (None, None, 'IsControl'), 4) |
| }}; |