| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000019 |
| sim_ticks 18517500 |
| final_tick 18517500 |
| sim_freq 1000000000000 |
| host_inst_rate 45460 |
| host_op_rate 53229 |
| host_tick_rate 183240261 |
| host_mem_usage 280812 |
| host_seconds 0.10 |
| sim_insts 4592 |
| sim_ops 5378 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.physmem.bytes_read::cpu.inst 17600 |
| system.physmem.bytes_read::cpu.data 7744 |
| system.physmem.bytes_read::total 25344 |
| system.physmem.bytes_inst_read::cpu.inst 17600 |
| system.physmem.bytes_inst_read::total 17600 |
| system.physmem.num_reads::cpu.inst 275 |
| system.physmem.num_reads::cpu.data 121 |
| system.physmem.num_reads::total 396 |
| system.physmem.bw_read::cpu.inst 950452275 |
| system.physmem.bw_read::cpu.data 418199001 |
| system.physmem.bw_read::total 1368651276 |
| system.physmem.bw_inst_read::cpu.inst 950452275 |
| system.physmem.bw_inst_read::total 950452275 |
| system.physmem.bw_total::cpu.inst 950452275 |
| system.physmem.bw_total::cpu.data 418199001 |
| system.physmem.bw_total::total 1368651276 |
| system.physmem.readReqs 396 |
| system.physmem.writeReqs 0 |
| system.physmem.readBursts 396 |
| system.physmem.writeBursts 0 |
| system.physmem.bytesReadDRAM 25344 |
| system.physmem.bytesReadWrQ 0 |
| system.physmem.bytesWritten 0 |
| system.physmem.bytesReadSys 25344 |
| system.physmem.bytesWrittenSys 0 |
| system.physmem.servicedByWrQ 0 |
| system.physmem.mergedWrBursts 0 |
| system.physmem.neitherReadNorWriteReqs 0 |
| system.physmem.perBankRdBursts::0 89 |
| system.physmem.perBankRdBursts::1 45 |
| system.physmem.perBankRdBursts::2 20 |
| system.physmem.perBankRdBursts::3 43 |
| system.physmem.perBankRdBursts::4 18 |
| system.physmem.perBankRdBursts::5 32 |
| system.physmem.perBankRdBursts::6 35 |
| system.physmem.perBankRdBursts::7 10 |
| system.physmem.perBankRdBursts::8 4 |
| system.physmem.perBankRdBursts::9 8 |
| system.physmem.perBankRdBursts::10 28 |
| system.physmem.perBankRdBursts::11 42 |
| system.physmem.perBankRdBursts::12 10 |
| system.physmem.perBankRdBursts::13 6 |
| system.physmem.perBankRdBursts::14 0 |
| system.physmem.perBankRdBursts::15 6 |
| system.physmem.perBankWrBursts::0 0 |
| system.physmem.perBankWrBursts::1 0 |
| system.physmem.perBankWrBursts::2 0 |
| system.physmem.perBankWrBursts::3 0 |
| system.physmem.perBankWrBursts::4 0 |
| system.physmem.perBankWrBursts::5 0 |
| system.physmem.perBankWrBursts::6 0 |
| system.physmem.perBankWrBursts::7 0 |
| system.physmem.perBankWrBursts::8 0 |
| system.physmem.perBankWrBursts::9 0 |
| system.physmem.perBankWrBursts::10 0 |
| system.physmem.perBankWrBursts::11 0 |
| system.physmem.perBankWrBursts::12 0 |
| system.physmem.perBankWrBursts::13 0 |
| system.physmem.perBankWrBursts::14 0 |
| system.physmem.perBankWrBursts::15 0 |
| system.physmem.numRdRetry 0 |
| system.physmem.numWrRetry 0 |
| system.physmem.totGap 18432000 |
| system.physmem.readPktSize::0 0 |
| system.physmem.readPktSize::1 0 |
| system.physmem.readPktSize::2 0 |
| system.physmem.readPktSize::3 0 |
| system.physmem.readPktSize::4 0 |
| system.physmem.readPktSize::5 0 |
| system.physmem.readPktSize::6 396 |
| system.physmem.writePktSize::0 0 |
| system.physmem.writePktSize::1 0 |
| system.physmem.writePktSize::2 0 |
| system.physmem.writePktSize::3 0 |
| system.physmem.writePktSize::4 0 |
| system.physmem.writePktSize::5 0 |
| system.physmem.writePktSize::6 0 |
| system.physmem.rdQLenPdf::0 204 |
| system.physmem.rdQLenPdf::1 121 |
| system.physmem.rdQLenPdf::2 52 |
| system.physmem.rdQLenPdf::3 14 |
| system.physmem.rdQLenPdf::4 4 |
| system.physmem.rdQLenPdf::5 1 |
| system.physmem.rdQLenPdf::6 0 |
| system.physmem.rdQLenPdf::7 0 |
| system.physmem.rdQLenPdf::8 0 |
| system.physmem.rdQLenPdf::9 0 |
| system.physmem.rdQLenPdf::10 0 |
| system.physmem.rdQLenPdf::11 0 |
| system.physmem.rdQLenPdf::12 0 |
| system.physmem.rdQLenPdf::13 0 |
| system.physmem.rdQLenPdf::14 0 |
| system.physmem.rdQLenPdf::15 0 |
| system.physmem.rdQLenPdf::16 0 |
| system.physmem.rdQLenPdf::17 0 |
| system.physmem.rdQLenPdf::18 0 |
| system.physmem.rdQLenPdf::19 0 |
| system.physmem.rdQLenPdf::20 0 |
| system.physmem.rdQLenPdf::21 0 |
| system.physmem.rdQLenPdf::22 0 |
| system.physmem.rdQLenPdf::23 0 |
| system.physmem.rdQLenPdf::24 0 |
| system.physmem.rdQLenPdf::25 0 |
| system.physmem.rdQLenPdf::26 0 |
| system.physmem.rdQLenPdf::27 0 |
| system.physmem.rdQLenPdf::28 0 |
| system.physmem.rdQLenPdf::29 0 |
| system.physmem.rdQLenPdf::30 0 |
| system.physmem.rdQLenPdf::31 0 |
| system.physmem.wrQLenPdf::0 0 |
| system.physmem.wrQLenPdf::1 0 |
| system.physmem.wrQLenPdf::2 0 |
| system.physmem.wrQLenPdf::3 0 |
| system.physmem.wrQLenPdf::4 0 |
| system.physmem.wrQLenPdf::5 0 |
| system.physmem.wrQLenPdf::6 0 |
| system.physmem.wrQLenPdf::7 0 |
| system.physmem.wrQLenPdf::8 0 |
| system.physmem.wrQLenPdf::9 0 |
| system.physmem.wrQLenPdf::10 0 |
| system.physmem.wrQLenPdf::11 0 |
| system.physmem.wrQLenPdf::12 0 |
| system.physmem.wrQLenPdf::13 0 |
| system.physmem.wrQLenPdf::14 0 |
| system.physmem.wrQLenPdf::15 0 |
| system.physmem.wrQLenPdf::16 0 |
| system.physmem.wrQLenPdf::17 0 |
| system.physmem.wrQLenPdf::18 0 |
| system.physmem.wrQLenPdf::19 0 |
| system.physmem.wrQLenPdf::20 0 |
| system.physmem.wrQLenPdf::21 0 |
| system.physmem.wrQLenPdf::22 0 |
| system.physmem.wrQLenPdf::23 0 |
| system.physmem.wrQLenPdf::24 0 |
| system.physmem.wrQLenPdf::25 0 |
| system.physmem.wrQLenPdf::26 0 |
| system.physmem.wrQLenPdf::27 0 |
| system.physmem.wrQLenPdf::28 0 |
| system.physmem.wrQLenPdf::29 0 |
| system.physmem.wrQLenPdf::30 0 |
| system.physmem.wrQLenPdf::31 0 |
| system.physmem.wrQLenPdf::32 0 |
| system.physmem.wrQLenPdf::33 0 |
| system.physmem.wrQLenPdf::34 0 |
| system.physmem.wrQLenPdf::35 0 |
| system.physmem.wrQLenPdf::36 0 |
| system.physmem.wrQLenPdf::37 0 |
| system.physmem.wrQLenPdf::38 0 |
| system.physmem.wrQLenPdf::39 0 |
| system.physmem.wrQLenPdf::40 0 |
| system.physmem.wrQLenPdf::41 0 |
| system.physmem.wrQLenPdf::42 0 |
| system.physmem.wrQLenPdf::43 0 |
| system.physmem.wrQLenPdf::44 0 |
| system.physmem.wrQLenPdf::45 0 |
| system.physmem.wrQLenPdf::46 0 |
| system.physmem.wrQLenPdf::47 0 |
| system.physmem.wrQLenPdf::48 0 |
| system.physmem.wrQLenPdf::49 0 |
| system.physmem.wrQLenPdf::50 0 |
| system.physmem.wrQLenPdf::51 0 |
| system.physmem.wrQLenPdf::52 0 |
| system.physmem.wrQLenPdf::53 0 |
| system.physmem.wrQLenPdf::54 0 |
| system.physmem.wrQLenPdf::55 0 |
| system.physmem.wrQLenPdf::56 0 |
| system.physmem.wrQLenPdf::57 0 |
| system.physmem.wrQLenPdf::58 0 |
| system.physmem.wrQLenPdf::59 0 |
| system.physmem.wrQLenPdf::60 0 |
| system.physmem.wrQLenPdf::61 0 |
| system.physmem.wrQLenPdf::62 0 |
| system.physmem.wrQLenPdf::63 0 |
| system.physmem.bytesPerActivate::samples 59 |
| system.physmem.bytesPerActivate::mean 406.779661 |
| system.physmem.bytesPerActivate::gmean 269.610222 |
| system.physmem.bytesPerActivate::stdev 346.645206 |
| system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% |
| system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% |
| system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% |
| system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% |
| system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% |
| system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% |
| system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% |
| system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% |
| system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% |
| system.physmem.bytesPerActivate::total 59 |
| system.physmem.totQLat 5212000 |
| system.physmem.totMemAccLat 12637000 |
| system.physmem.totBusLat 1980000 |
| system.physmem.avgQLat 13161.62 |
| system.physmem.avgBusLat 5000.00 |
| system.physmem.avgMemAccLat 31911.62 |
| system.physmem.avgRdBW 1368.65 |
| system.physmem.avgWrBW 0.00 |
| system.physmem.avgRdBWSys 1368.65 |
| system.physmem.avgWrBWSys 0.00 |
| system.physmem.peakBW 12800.00 |
| system.physmem.busUtil 10.69 |
| system.physmem.busUtilRead 10.69 |
| system.physmem.busUtilWrite 0.00 |
| system.physmem.avgRdQLen 1.87 |
| system.physmem.avgWrQLen 0.00 |
| system.physmem.readRowHits 329 |
| system.physmem.writeRowHits 0 |
| system.physmem.readRowHitRate 83.08 |
| system.physmem.writeRowHitRate nan |
| system.physmem.avgGap 46545.45 |
| system.physmem.pageHitRate 83.08 |
| system.physmem_0.actEnergy 314160 |
| system.physmem_0.preEnergy 151800 |
| system.physmem_0.readEnergy 2084880 |
| system.physmem_0.writeEnergy 0 |
| system.physmem_0.refreshEnergy 1229280.000000 |
| system.physmem_0.actBackEnergy 3085980 |
| system.physmem_0.preBackEnergy 37920 |
| system.physmem_0.actPowerDownEnergy 5290170 |
| system.physmem_0.prePowerDownEnergy 19200 |
| system.physmem_0.selfRefreshEnergy 0 |
| system.physmem_0.totalEnergy 12213390 |
| system.physmem_0.averagePower 659.559336 |
| system.physmem_0.totalIdleTime 11496500 |
| system.physmem_0.memoryStateTime::IDLE 29500 |
| system.physmem_0.memoryStateTime::REF 520000 |
| system.physmem_0.memoryStateTime::SREF 0 |
| system.physmem_0.memoryStateTime::PRE_PDN 49250 |
| system.physmem_0.memoryStateTime::ACT 6316250 |
| system.physmem_0.memoryStateTime::ACT_PDN 11602500 |
| system.physmem_1.actEnergy 164220 |
| system.physmem_1.preEnergy 72105 |
| system.physmem_1.readEnergy 742560 |
| system.physmem_1.writeEnergy 0 |
| system.physmem_1.refreshEnergy 1229280.000000 |
| system.physmem_1.actBackEnergy 1457490 |
| system.physmem_1.preBackEnergy 66240 |
| system.physmem_1.actPowerDownEnergy 6092730 |
| system.physmem_1.prePowerDownEnergy 686400 |
| system.physmem_1.selfRefreshEnergy 0 |
| system.physmem_1.totalEnergy 10511025 |
| system.physmem_1.averagePower 567.626569 |
| system.physmem_1.totalIdleTime 15098500 |
| system.physmem_1.memoryStateTime::IDLE 116000 |
| system.physmem_1.memoryStateTime::REF 520000 |
| system.physmem_1.memoryStateTime::SREF 0 |
| system.physmem_1.memoryStateTime::PRE_PDN 1787250 |
| system.physmem_1.memoryStateTime::ACT 2733750 |
| system.physmem_1.memoryStateTime::ACT_PDN 13360500 |
| system.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.branchPred.lookups 2820 |
| system.cpu.branchPred.condPredicted 1728 |
| system.cpu.branchPred.condIncorrect 468 |
| system.cpu.branchPred.BTBLookups 2384 |
| system.cpu.branchPred.BTBHits 844 |
| system.cpu.branchPred.BTBCorrect 0 |
| system.cpu.branchPred.BTBHitPct 35.402685 |
| system.cpu.branchPred.usedRAS 322 |
| system.cpu.branchPred.RASInCorrect 70 |
| system.cpu.branchPred.indirectLookups 260 |
| system.cpu.branchPred.indirectHits 13 |
| system.cpu.branchPred.indirectMisses 247 |
| system.cpu.branchPredindirectMispredicted 64 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.checker.dtb.walker.walks 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.checker.dtb.inst_hits 0 |
| system.cpu.checker.dtb.inst_misses 0 |
| system.cpu.checker.dtb.read_hits 0 |
| system.cpu.checker.dtb.read_misses 0 |
| system.cpu.checker.dtb.write_hits 0 |
| system.cpu.checker.dtb.write_misses 0 |
| system.cpu.checker.dtb.flush_tlb 0 |
| system.cpu.checker.dtb.flush_tlb_mva 0 |
| system.cpu.checker.dtb.flush_tlb_mva_asid 0 |
| system.cpu.checker.dtb.flush_tlb_asid 0 |
| system.cpu.checker.dtb.flush_entries 0 |
| system.cpu.checker.dtb.align_faults 0 |
| system.cpu.checker.dtb.prefetch_faults 0 |
| system.cpu.checker.dtb.domain_faults 0 |
| system.cpu.checker.dtb.perms_faults 0 |
| system.cpu.checker.dtb.read_accesses 0 |
| system.cpu.checker.dtb.write_accesses 0 |
| system.cpu.checker.dtb.inst_accesses 0 |
| system.cpu.checker.dtb.hits 0 |
| system.cpu.checker.dtb.misses 0 |
| system.cpu.checker.dtb.accesses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.checker.itb.walker.walks 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.checker.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.checker.itb.inst_hits 0 |
| system.cpu.checker.itb.inst_misses 0 |
| system.cpu.checker.itb.read_hits 0 |
| system.cpu.checker.itb.read_misses 0 |
| system.cpu.checker.itb.write_hits 0 |
| system.cpu.checker.itb.write_misses 0 |
| system.cpu.checker.itb.flush_tlb 0 |
| system.cpu.checker.itb.flush_tlb_mva 0 |
| system.cpu.checker.itb.flush_tlb_mva_asid 0 |
| system.cpu.checker.itb.flush_tlb_asid 0 |
| system.cpu.checker.itb.flush_entries 0 |
| system.cpu.checker.itb.align_faults 0 |
| system.cpu.checker.itb.prefetch_faults 0 |
| system.cpu.checker.itb.domain_faults 0 |
| system.cpu.checker.itb.perms_faults 0 |
| system.cpu.checker.itb.read_accesses 0 |
| system.cpu.checker.itb.write_accesses 0 |
| system.cpu.checker.itb.inst_accesses 0 |
| system.cpu.checker.itb.hits 0 |
| system.cpu.checker.itb.misses 0 |
| system.cpu.checker.itb.accesses 0 |
| system.cpu.workload.numSyscalls 13 |
| system.cpu.checker.pwrStateResidencyTicks::ON 18517500 |
| system.cpu.checker.numCycles 5391 |
| system.cpu.checker.numWorkItemsStarted 0 |
| system.cpu.checker.numWorkItemsCompleted 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.pwrStateResidencyTicks::ON 18517500 |
| system.cpu.numCycles 37036 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.fetch.icacheStallCycles 7733 |
| system.cpu.fetch.Insts 12373 |
| system.cpu.fetch.Branches 2820 |
| system.cpu.fetch.predictedBranches 1179 |
| system.cpu.fetch.Cycles 5113 |
| system.cpu.fetch.SquashCycles 984 |
| system.cpu.fetch.MiscStallCycles 1 |
| system.cpu.fetch.PendingTrapStallCycles 260 |
| system.cpu.fetch.IcacheWaitRetryStallCycles 17 |
| system.cpu.fetch.CacheLines 1982 |
| system.cpu.fetch.IcacheSquashes 291 |
| system.cpu.fetch.rateDist::samples 13616 |
| system.cpu.fetch.rateDist::mean 1.093052 |
| system.cpu.fetch.rateDist::stdev 2.461769 |
| system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu.fetch.rateDist::0 10916 80.17% 80.17% |
| system.cpu.fetch.rateDist::1 271 1.99% 82.16% |
| system.cpu.fetch.rateDist::2 182 1.34% 83.50% |
| system.cpu.fetch.rateDist::3 206 1.51% 85.01% |
| system.cpu.fetch.rateDist::4 259 1.90% 86.91% |
| system.cpu.fetch.rateDist::5 398 2.92% 89.84% |
| system.cpu.fetch.rateDist::6 138 1.01% 90.85% |
| system.cpu.fetch.rateDist::7 192 1.41% 92.26% |
| system.cpu.fetch.rateDist::8 1054 7.74% 100.00% |
| system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu.fetch.rateDist::min_value 0 |
| system.cpu.fetch.rateDist::max_value 8 |
| system.cpu.fetch.rateDist::total 13616 |
| system.cpu.fetch.branchRate 0.076142 |
| system.cpu.fetch.rate 0.334080 |
| system.cpu.decode.IdleCycles 6341 |
| system.cpu.decode.BlockedCycles 4657 |
| system.cpu.decode.RunCycles 2138 |
| system.cpu.decode.UnblockCycles 142 |
| system.cpu.decode.SquashCycles 338 |
| system.cpu.decode.BranchResolved 909 |
| system.cpu.decode.BranchMispred 160 |
| system.cpu.decode.DecodedInsts 12250 |
| system.cpu.decode.SquashedInsts 489 |
| system.cpu.rename.SquashCycles 338 |
| system.cpu.rename.IdleCycles 6573 |
| system.cpu.rename.BlockCycles 835 |
| system.cpu.rename.serializeStallCycles 2470 |
| system.cpu.rename.RunCycles 2036 |
| system.cpu.rename.UnblockCycles 1364 |
| system.cpu.rename.RenamedInsts 11552 |
| system.cpu.rename.ROBFullEvents 4 |
| system.cpu.rename.IQFullEvents 181 |
| system.cpu.rename.LQFullEvents 144 |
| system.cpu.rename.SQFullEvents 1170 |
| system.cpu.rename.RenamedOperands 11673 |
| system.cpu.rename.RenameLookups 53030 |
| system.cpu.rename.int_rename_lookups 12530 |
| system.cpu.rename.fp_rename_lookups 199 |
| system.cpu.rename.CommittedMaps 5494 |
| system.cpu.rename.UndoneMaps 6179 |
| system.cpu.rename.serializingInsts 40 |
| system.cpu.rename.tempSerializingInsts 34 |
| system.cpu.rename.skidInsts 442 |
| system.cpu.memDep0.insertedLoads 2293 |
| system.cpu.memDep0.insertedStores 1619 |
| system.cpu.memDep0.conflictingLoads 33 |
| system.cpu.memDep0.conflictingStores 22 |
| system.cpu.iq.iqInstsAdded 10296 |
| system.cpu.iq.iqNonSpecInstsAdded 44 |
| system.cpu.iq.iqInstsIssued 8207 |
| system.cpu.iq.iqSquashedInstsIssued 43 |
| system.cpu.iq.iqSquashedInstsExamined 4961 |
| system.cpu.iq.iqSquashedOperandsExamined 12830 |
| system.cpu.iq.iqSquashedNonSpecRemoved 7 |
| system.cpu.iq.issued_per_cycle::samples 13616 |
| system.cpu.iq.issued_per_cycle::mean 0.602747 |
| system.cpu.iq.issued_per_cycle::stdev 1.340306 |
| system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% |
| system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% |
| system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% |
| system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% |
| system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% |
| system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% |
| system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% |
| system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% |
| system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% |
| system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::min_value 0 |
| system.cpu.iq.issued_per_cycle::max_value 8 |
| system.cpu.iq.issued_per_cycle::total 13616 |
| system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% |
| system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% |
| system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% |
| system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% |
| system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% |
| system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% |
| system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% |
| system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% |
| system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% |
| system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% |
| system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% |
| system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% |
| system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% |
| system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% |
| system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% |
| system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% |
| system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% |
| system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% |
| system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% |
| system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% |
| system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::total 8207 |
| system.cpu.iq.rate 0.221595 |
| system.cpu.iq.fu_busy_cnt 166 |
| system.cpu.iq.fu_busy_rate 0.020227 |
| system.cpu.iq.int_inst_queue_reads 30145 |
| system.cpu.iq.int_inst_queue_writes 15188 |
| system.cpu.iq.int_inst_queue_wakeup_accesses 7438 |
| system.cpu.iq.fp_inst_queue_reads 94 |
| system.cpu.iq.fp_inst_queue_writes 132 |
| system.cpu.iq.fp_inst_queue_wakeup_accesses 32 |
| system.cpu.iq.int_alu_accesses 8327 |
| system.cpu.iq.fp_alu_accesses 46 |
| system.cpu.iew.lsq.thread0.forwLoads 24 |
| system.cpu.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu.iew.lsq.thread0.squashedLoads 1266 |
| system.cpu.iew.lsq.thread0.ignoredResponses 0 |
| system.cpu.iew.lsq.thread0.memOrderViolation 19 |
| system.cpu.iew.lsq.thread0.squashedStores 681 |
| system.cpu.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu.iew.lsq.thread0.blockedLoads 0 |
| system.cpu.iew.lsq.thread0.rescheduledLoads 32 |
| system.cpu.iew.lsq.thread0.cacheBlocked 4 |
| system.cpu.iew.iewIdleCycles 0 |
| system.cpu.iew.iewSquashCycles 338 |
| system.cpu.iew.iewBlockCycles 707 |
| system.cpu.iew.iewUnblockCycles 17 |
| system.cpu.iew.iewDispatchedInsts 10349 |
| system.cpu.iew.iewDispSquashedInsts 128 |
| system.cpu.iew.iewDispLoadInsts 2293 |
| system.cpu.iew.iewDispStoreInsts 1619 |
| system.cpu.iew.iewDispNonSpecInsts 32 |
| system.cpu.iew.iewIQFullEvents 12 |
| system.cpu.iew.iewLSQFullEvents 4 |
| system.cpu.iew.memOrderViolationEvents 19 |
| system.cpu.iew.predictedTakenIncorrect 93 |
| system.cpu.iew.predictedNotTakenIncorrect 267 |
| system.cpu.iew.branchMispredicts 360 |
| system.cpu.iew.iewExecutedInsts 7885 |
| system.cpu.iew.iewExecLoadInsts 1840 |
| system.cpu.iew.iewExecSquashedInsts 322 |
| system.cpu.iew.exec_swp 0 |
| system.cpu.iew.exec_nop 9 |
| system.cpu.iew.exec_refs 3007 |
| system.cpu.iew.exec_branches 1490 |
| system.cpu.iew.exec_stores 1167 |
| system.cpu.iew.exec_rate 0.212901 |
| system.cpu.iew.wb_sent 7581 |
| system.cpu.iew.wb_count 7470 |
| system.cpu.iew.wb_producers 3518 |
| system.cpu.iew.wb_consumers 6872 |
| system.cpu.iew.wb_rate 0.201696 |
| system.cpu.iew.wb_fanout 0.511932 |
| system.cpu.commit.commitSquashedInsts 4970 |
| system.cpu.commit.commitNonSpecStalls 37 |
| system.cpu.commit.branchMispredicts 314 |
| system.cpu.commit.committed_per_cycle::samples 12743 |
| system.cpu.commit.committed_per_cycle::mean 0.422036 |
| system.cpu.commit.committed_per_cycle::stdev 1.264076 |
| system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% |
| system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% |
| system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% |
| system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% |
| system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% |
| system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% |
| system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% |
| system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% |
| system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% |
| system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu.commit.committed_per_cycle::min_value 0 |
| system.cpu.commit.committed_per_cycle::max_value 8 |
| system.cpu.commit.committed_per_cycle::total 12743 |
| system.cpu.commit.committedInsts 4592 |
| system.cpu.commit.committedOps 5378 |
| system.cpu.commit.swp_count 0 |
| system.cpu.commit.refs 1965 |
| system.cpu.commit.loads 1027 |
| system.cpu.commit.membars 12 |
| system.cpu.commit.branches 1008 |
| system.cpu.commit.fp_insts 16 |
| system.cpu.commit.int_insts 4624 |
| system.cpu.commit.function_calls 82 |
| system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% |
| system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% |
| system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% |
| system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% |
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| system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% |
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| system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% |
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| system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% |
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| system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% |
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| system.cpu.l2cache.overall_miss_rate::total 0.913636 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 |
| system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 |
| system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 |
| system.cpu.l2cache.demand_mshr_hits::cpu.data 6 |
| system.cpu.l2cache.demand_mshr_hits::total 6 |
| system.cpu.l2cache.overall_mshr_hits::cpu.data 6 |
| system.cpu.l2cache.overall_mshr_hits::total 6 |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 42 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 121 |
| system.cpu.l2cache.demand_mshr_misses::total 396 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 121 |
| system.cpu.l2cache.overall_mshr_misses::total 396 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 442 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 398 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 2 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 42 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 42 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 |
| system.cpu.toL2Bus.pkt_count::total 882 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 |
| system.cpu.toL2Bus.pkt_size::total 28288 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 440 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.100000 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% |
| system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 |
| system.cpu.toL2Bus.snoop_fanout::total 440 |
| system.cpu.toL2Bus.reqLayer0.occupancy 223000 |
| system.cpu.toL2Bus.reqLayer0.utilization 1.2 |
| system.cpu.toL2Bus.respLayer0.occupancy 439500 |
| system.cpu.toL2Bus.respLayer0.utilization 2.4 |
| system.cpu.toL2Bus.respLayer1.occupancy 223494 |
| system.cpu.toL2Bus.respLayer1.utilization 1.2 |
| system.membus.snoop_filter.tot_requests 396 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 |
| system.membus.trans_dist::ReadResp 354 |
| system.membus.trans_dist::ReadExReq 42 |
| system.membus.trans_dist::ReadExResp 42 |
| system.membus.trans_dist::ReadSharedReq 354 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 |
| system.membus.pkt_count::total 792 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 |
| system.membus.pkt_size::total 25344 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 396 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 396 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 396 |
| system.membus.reqLayer0.occupancy 484000 |
| system.membus.reqLayer0.utilization 2.6 |
| system.membus.respLayer1.occupancy 2091500 |
| system.membus.respLayer1.utilization 11.3 |
| |
| ---------- End Simulation Statistics ---------- |