commit e758cd09d8163c2352aca8a7336c8d84d4cd0975
author Gabe Black <gabeblack@google.com> Mon Nov 25 16:38:22 2019 -0800
committer Gabe Black <gabeblack@google.com> Fri Feb 07 07:39:47 2020 +0000
tree bd22f4a008d5a67d9b71730e41441fa93a131006
parent 95c6a839a5f58914eca4d77afe2150eec4eac7e7

x86: Use the m5 op range in the system.

Don't hard code a range into the TLB.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0ead4353672ccf6e3e51ddbb4676be3a09f1136a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23182
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

src/arch/x86/X86TLB.py

diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 2e61d02..b3200ec 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -55,5 +55,6 @@
     cxx_class = 'X86ISA::TLB'
     cxx_header = 'arch/x86/tlb.hh'
     size = Param.Unsigned(64, "TLB size")
+    system = Param.System(Parent.any, "system object")
     walker = Param.X86PagetableWalker(\
             X86PagetableWalker(), "page table walker")

src/arch/x86/tlb.cc

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 2985a8b..65ed9c0 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -61,7 +61,7 @@
 
 TLB::TLB(const Params *p)
     : BaseTLB(p), configAddress(0), size(p->size),
-      tlb(size), lruSeq(0)
+      tlb(size), lruSeq(0), m5opRange(p->system->m5opRange())
 {
     if (!size)
         fatal("TLBs must have a non-zero size.\n");
@@ -229,8 +229,6 @@
 {
     Addr paddr = req->getPaddr();
 
-    AddrRange m5opRange(0xFFFF0000, 0x100000000);
-
     if (m5opRange.contains(paddr)) {
         req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
                       Request::STRICT_ORDER);

src/arch/x86/tlb.hh

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index b969bca..21bd640 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,8 @@
         TlbEntryTrie trie;
         uint64_t lruSeq;
 
+        AddrRange m5opRange;
+
         // Statistics
         Stats::Scalar rdAccesses;
         Stats::Scalar wrAccesses;