commit e7c75d2c114836203fb5c4d0a7d842c4f4ebaa0e
author Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Sep 02 11:26:15 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 20:00:34 2019 +0000
tree ef1931b5aaad562807fdd2cec75b80dbcf4331a0
parent 2a818db77ab5fe5cc7d716dd2aa88241550045a7

dev-arm: State update when setting MISCREG_ICC_IGRPENx register

This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).

Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index b793f7c..0cb0367 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -1321,7 +1321,9 @@
               return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
           }
 
-          break;
+          isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN0_EL1, val);
+          updateDistributor();
+          return;
       }
 
       // Virtual Interrupt Group 0 Enable register
@@ -1360,6 +1362,7 @@
           }
 
           setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
+          updateDistributor();
           return;
       }