src/dev/riscv/Plic.py

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from m5.objects.Device import BasicPioDevice
from m5.params import *
from m5.proxy import *
from m5.util.fdthelper import *


class PlicBase(BasicPioDevice):
    """
    This is abstract class of PLIC and
    define interface to handle received
    interrupt singal from device
    """

    type = "PlicBase"
    cxx_header = "dev/riscv/plic.hh"
    cxx_class = "gem5::PlicBase"
    abstract = True

    pio_size = Param.Addr("PIO Size")


class Plic(PlicBase):
    """
    This implementation of PLIC is based on
    the SiFive U54MC datasheet:
    https://sifive.cdn.prismic.io/sifive/fab000f6-
    0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_
    full_20G1.03.00_manual.pdf
    """

    type = "Plic"
    cxx_header = "dev/riscv/plic.hh"
    cxx_class = "gem5::Plic"
    pio_size = 0x4000000
    n_src = Param.Int("Number of interrupt sources")
    n_contexts = Param.Int(
        "Number of interrupt contexts. Usually the number "
        "of threads * 2. One for M mode, one for S mode"
    )

    def generateDeviceTree(self, state):
        node = self.generateBasicPioDeviceNode(
            state, "plic", self.pio_addr, self.pio_size
        )

        int_state = FdtState(addr_cells=0, interrupt_cells=1)
        node.append(int_state.addrCellsProperty())
        node.append(int_state.interruptCellsProperty())

        phandle = int_state.phandle(self)
        node.append(FdtPropertyWords("phandle", [phandle]))
        node.append(FdtPropertyWords("riscv,ndev", [self.n_src - 1]))

        cpus = self.system.unproxy(self).cpu
        int_extended = list()
        for cpu in cpus:
            phandle = int_state.phandle(cpu)
            int_extended.append(phandle)
            int_extended.append(0xB)
            int_extended.append(phandle)
            int_extended.append(0x9)

        node.append(FdtPropertyWords("interrupts-extended", int_extended))
        node.append(FdtProperty("interrupt-controller"))
        node.appendCompatible(["riscv,plic0"])

        yield node