commit eb0b4ba65793316f188e33de7f70fb1aa4502d7c
author Tiago Mück <tiago.muck@arm.com> Wed Sep 22 14:05:28 2021 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Apr 12 10:21:57 2022 +0000
tree d5f3a713db51eb7925e79bc69472847c56639f2a
parent bb45503c5f96c2c1ac0229607adb53047ffeb082

mem-ruby: CHI fix for WUs on local+upstream line

Fix for WriteUnique operations on cache lines that are both local and
upstream

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57299
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
index c4eb8ff..0f1a7c6 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -337,7 +337,7 @@
 
 // WriteUniquePtl
 
-transition({UD,UD_RU,UD_RSD,UD_RSC,UC,UC_RU,UC_RSC},
+transition({UD,UD_RSD,UD_RSC,UC,UC_RSC},
            {WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC, WriteUniqueFull_PoC_Alloc},
            BUSY_BLKD) {
   Initiate_Request;
@@ -347,6 +347,16 @@
   ProcessNextState;
 }
 
+transition({UD_RU,UC_RU},
+           {WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC, WriteUniqueFull_PoC_Alloc},
+           BUSY_BLKD) {
+  Initiate_Request;
+  Initiate_WriteUnique_LocalWrite;
+  Profile_Miss;
+  Pop_ReqRdyQueue;
+  ProcessNextState;
+}
+
 transition({SD, SD_RSD, SD_RSC, SC, SC_RSC},
            {WriteUniquePtl_PoC, WriteUniqueFull_PoC, WriteUniqueFull_PoC_Alloc},
            BUSY_BLKD) {