dev-arm: Limit number of max PE in GICv3 to 128
This is needed since there is a problem in the memory layout of
VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping
regions when reserving space for 256 PEs.
GICv3 redistributors: 0x2c010000 - 0x30010000
PCI regions: 0x30000000 - 0x40000000
We fix this by cutting down the number of supported PEs to 128
Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 9086448..f83f075 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1085,6 +1085,9 @@
class VExpress_GEM5_V2_Base(VExpress_GEM5_Base):
gic = Gicv3(maint_int=ArmPPI(num=25))
+ # Limiting to 128 since it will otherwise overlap with PCI space
+ gic.cpu_max = 128
+
def _on_chip_devices(self):
return super(VExpress_GEM5_V2_Base,self)._on_chip_devices() + [
self.gic,
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
index 1dc235d..9cdee85 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
@@ -40,9 +40,9 @@
#interrupt-cells = <0x3>;
#address-cells = <0x2>;
interrupt-controller;
- redistributor-stride = <0x0 0x40000>; // 256kB stride, needed for ARM AVS tests...
+ redistributor-stride = <0x0 0x40000>; // 256kB stride
reg = <0x0 0x2c000000 0x0 0x10000
- 0x0 0x2c010000 0x0 0x4000000 // room for 256 redistributors using 128K each (256K strided...)
+ 0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...)
0x0 0x0 0x0 0x0>;
interrupts = <1 9 0xf04>;
#size-cells = <0x2>;
