| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| exit_on_work_items=false |
| init_param=0 |
| kernel= |
| kernel_addr_check=true |
| load_addr_mask=1099511627775 |
| load_offset=0 |
| mem_mode=timing |
| mem_ranges=0:536870911:0:0:0:0 |
| memories=system.mem_ctrl |
| mmap_using_noreserve=false |
| multi_thread=false |
| num_work_ids=16 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| readfile= |
| symbolfile= |
| thermal_components= |
| thermal_model=Null |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[1] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| children=voltage_domain |
| clock=1000 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.clk_domain.voltage_domain |
| |
| [system.clk_domain.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |
| [system.cpu] |
| type=TimingSimpleCPU |
| children=dcache dtb icache interrupts isa itb tracer workload |
| branchPred=Null |
| checker=Null |
| clk_domain=system.clk_domain |
| cpu_id=-1 |
| default_p_state=UNDEFINED |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dtb=system.cpu.dtb |
| eventq_index=0 |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu.interrupts |
| isa=system.cpu.isa |
| itb=system.cpu.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| profile=0 |
| progress_interval=0 |
| simpoint_start_insts= |
| socket_id=0 |
| switched_out=false |
| system=system |
| tracer=system.cpu.tracer |
| workload=system.cpu.workload |
| dcache_port=system.cpu.dcache.cpu_side |
| icache_port=system.cpu.icache.cpu_side |
| |
| [system.cpu.dcache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=2 |
| clk_domain=system.clk_domain |
| clusivity=mostly_incl |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| hit_latency=2 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=4 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=65536 |
| system=system |
| tags=system.cpu.dcache.tags |
| tgts_per_mshr=20 |
| write_buffers=8 |
| writeback_clean=false |
| cpu_side=system.cpu.dcache_port |
| mem_side=system.l2bus.slave[1] |
| |
| [system.cpu.dcache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| hit_latency=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=65536 |
| |
| [system.cpu.dtb] |
| type=MipsTLB |
| eventq_index=0 |
| size=64 |
| |
| [system.cpu.icache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=2 |
| clk_domain=system.clk_domain |
| clusivity=mostly_incl |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| hit_latency=2 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=4 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=16384 |
| system=system |
| tags=system.cpu.icache.tags |
| tgts_per_mshr=20 |
| write_buffers=8 |
| writeback_clean=false |
| cpu_side=system.cpu.icache_port |
| mem_side=system.l2bus.slave[0] |
| |
| [system.cpu.icache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| hit_latency=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=16384 |
| |
| [system.cpu.interrupts] |
| type=MipsInterrupts |
| eventq_index=0 |
| |
| [system.cpu.isa] |
| type=MipsISA |
| eventq_index=0 |
| num_threads=1 |
| num_vpes=1 |
| system=system |
| |
| [system.cpu.itb] |
| type=MipsTLB |
| eventq_index=0 |
| size=64 |
| |
| [system.cpu.tracer] |
| type=ExeTracer |
| eventq_index=0 |
| |
| [system.cpu.workload] |
| type=LiveProcess |
| cmd=tests/test-progs/hello/bin/mips/linux/hello |
| cwd= |
| drivers= |
| egid=100 |
| env= |
| errout=cerr |
| euid=100 |
| eventq_index=0 |
| executable= |
| gid=100 |
| input=cin |
| kvmInSE=false |
| max_stack_size=67108864 |
| output=cout |
| pid=100 |
| ppid=99 |
| simpoint=0 |
| system=system |
| uid=100 |
| useArchPT=false |
| |
| [system.dvfs_handler] |
| type=DVFSHandler |
| domains= |
| enable=false |
| eventq_index=0 |
| sys_clk_domain=system.clk_domain |
| transition_latency=100000000 |
| |
| [system.l2bus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=0 |
| frontend_latency=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=false |
| power_model=Null |
| response_latency=1 |
| snoop_filter=system.l2bus.snoop_filter |
| snoop_response_latency=1 |
| system=system |
| use_default_range=false |
| width=32 |
| master=system.l2cache.cpu_side |
| slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side |
| |
| [system.l2bus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=0 |
| max_capacity=8388608 |
| system=system |
| |
| [system.l2cache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=8 |
| clk_domain=system.clk_domain |
| clusivity=mostly_incl |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| hit_latency=20 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=20 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=20 |
| sequential_access=false |
| size=262144 |
| system=system |
| tags=system.l2cache.tags |
| tgts_per_mshr=12 |
| write_buffers=8 |
| writeback_clean=false |
| cpu_side=system.l2bus.master[0] |
| mem_side=system.membus.slave[0] |
| |
| [system.l2cache.tags] |
| type=LRU |
| assoc=8 |
| block_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| hit_latency=20 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=262144 |
| |
| [system.mem_ctrl] |
| type=DRAMCtrl |
| IDD0=0.055000 |
| IDD02=0.000000 |
| IDD2N=0.032000 |
| IDD2N2=0.000000 |
| IDD2P0=0.000000 |
| IDD2P02=0.000000 |
| IDD2P1=0.032000 |
| IDD2P12=0.000000 |
| IDD3N=0.038000 |
| IDD3N2=0.000000 |
| IDD3P0=0.000000 |
| IDD3P02=0.000000 |
| IDD3P1=0.038000 |
| IDD3P12=0.000000 |
| IDD4R=0.157000 |
| IDD4R2=0.000000 |
| IDD4W=0.125000 |
| IDD4W2=0.000000 |
| IDD5=0.235000 |
| IDD52=0.000000 |
| IDD6=0.020000 |
| IDD62=0.000000 |
| VDD=1.500000 |
| VDD2=0.000000 |
| activation_limit=4 |
| addr_mapping=RoRaBaCoCh |
| bank_groups_per_rank=0 |
| banks_per_rank=8 |
| burst_length=8 |
| channels=1 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| default_p_state=UNDEFINED |
| device_bus_width=8 |
| device_rowbuffer_size=1024 |
| device_size=536870912 |
| devices_per_rank=8 |
| dll=true |
| eventq_index=0 |
| in_addr_map=true |
| kvm_map=true |
| max_accesses_per_row=16 |
| mem_sched_policy=frfcfs |
| min_writes_per_switch=16 |
| null=false |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| page_policy=open_adaptive |
| power_model=Null |
| range=0:536870911:0:0:0:0 |
| ranks_per_channel=2 |
| read_buffer_size=32 |
| static_backend_latency=10000 |
| static_frontend_latency=10000 |
| tBURST=5000 |
| tCCD_L=0 |
| tCK=1250 |
| tCL=13750 |
| tCS=2500 |
| tRAS=35000 |
| tRCD=13750 |
| tREFI=7800000 |
| tRFC=260000 |
| tRP=13750 |
| tRRD=6000 |
| tRRD_L=0 |
| tRTP=7500 |
| tRTW=2500 |
| tWR=15000 |
| tWTR=7500 |
| tXAW=30000 |
| tXP=6000 |
| tXPDLL=0 |
| tXS=270000 |
| tXSDLL=0 |
| write_buffer_size=64 |
| write_high_thresh_perc=85 |
| write_low_thresh_perc=50 |
| port=system.membus.master[0] |
| |
| [system.membus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=4 |
| frontend_latency=3 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=true |
| power_model=Null |
| response_latency=2 |
| snoop_filter=system.membus.snoop_filter |
| snoop_response_latency=4 |
| system=system |
| use_default_range=false |
| width=16 |
| master=system.mem_ctrl.port |
| slave=system.l2cache.mem_side system.system_port |
| |
| [system.membus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=1 |
| max_capacity=8388608 |
| system=system |
| |
