src/mem/port_proxy.hh

/*
 * Copyright (c) 2011-2013, 2018 ARM Limited
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 * notice, this list of conditions and the following disclaimer;
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 * this software without specific prior written permission.
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *
 * Authors: Andreas Hansson
 */

/**
 * @file
 * PortProxy Object Declaration.
 *
 * Port proxies are used when non-structural entities need access to
 * the memory system (or structural entities that want to peak into
 * the memory system without making a real memory access).
 *
 * Proxy objects replace the previous FunctionalPort, TranslatingPort
 * and VirtualPort objects, which provided the same functionality as
 * the proxies, but were instances of ports not corresponding to real
 * structural ports of the simulated system. Via the port proxies all
 * the accesses go through an actual port (either the system port,
 * e.g. for processes or initialisation, or a the data port of the
 * CPU, e.g. for threads) and thus are transparent to a potentially
 * distributed memory and automatically adhere to the memory map of
 * the system.
 */

#ifndef __MEM_PORT_PROXY_HH__
#define __MEM_PORT_PROXY_HH__

#include "mem/port.hh"
#include "sim/byteswap.hh"

/**
 * This object is a proxy for a structural port, to be used for debug
 * accesses.
 *
 * This proxy object is used when non structural entities
 * (e.g. thread contexts, object file loaders) need access to the
 * memory system. It calls the corresponding functions on the underlying
 * structural port, and provides templatized convenience access functions.
 *
 * The addresses are interpreted as physical addresses.
 *
 * @sa SETranslatingProxy
 * @sa FSTranslatingProxy
 */
class PortProxy
{
  private:

    /** The actual physical port used by this proxy. */
    MasterPort &_port;

    /** Granularity of any transactions issued through this proxy. */
    const unsigned int _cacheLineSize;

  public:
    PortProxy(MasterPort &port, unsigned int cacheLineSize) :
        _port(port), _cacheLineSize(cacheLineSize)
    {}
    virtual ~PortProxy() { }

    /**
     * Read size bytes memory at address and store in p.
     */
    virtual void
    readBlob(Addr addr, uint8_t* p, int size) const
    {
        readBlobPhys(addr, 0, p, size);
    }

    /**
     * Write size bytes from p to address.
     */
    virtual void
    writeBlob(Addr addr, const uint8_t* p, int size) const
    {
        writeBlobPhys(addr, 0, p, size);
    }

    /**
     * Fill size bytes starting at addr with byte value val.
     */
    virtual void
    memsetBlob(Addr addr, uint8_t v, int size) const
    {
        memsetBlobPhys(addr, 0, v, size);
    }

    /**
     * Read size bytes memory at physical address and store in p.
     */
    void readBlobPhys(Addr addr, Request::Flags flags,
                      uint8_t* p, int size) const;

    /**
     * Write size bytes from p to physical address.
     */
    void writeBlobPhys(Addr addr, Request::Flags flags,
                       const uint8_t* p, int size) const;

    /**
     * Fill size bytes starting at physical addr with byte value val.
     */
    void memsetBlobPhys(Addr addr, Request::Flags flags,
                        uint8_t v, int size) const;

    /**
     * Read sizeof(T) bytes from address and return as object T.
     */
    template <typename T>
    T read(Addr address) const;

    /**
     * Write object T to address. Writes sizeof(T) bytes.
     */
    template <typename T>
    void write(Addr address, T data) const;

    /**
     * Read sizeof(T) bytes from address and return as object T.
     * Performs endianness conversion from the selected guest to host order.
     */
    template <typename T>
    T read(Addr address, ByteOrder guest_byte_order) const;

    /**
     * Write object T to address. Writes sizeof(T) bytes.
     * Performs endianness conversion from host to the selected guest order.
     */
    template <typename T>
    void write(Addr address, T data, ByteOrder guest_byte_order) const;
};


/**
 * This object is a proxy for a structural port, to be used for debug
 * accesses to secure memory.
 *
 * The addresses are interpreted as physical addresses to secure memory.
 */
class SecurePortProxy : public PortProxy
{
  public:
    SecurePortProxy(MasterPort &port, unsigned int cache_line_size)
        : PortProxy(port, cache_line_size) {}

    void readBlob(Addr addr, uint8_t *p, int size) const override;
    void writeBlob(Addr addr, const uint8_t *p, int size) const override;
    void memsetBlob(Addr addr, uint8_t val, int size) const override;
};

template <typename T>
T
PortProxy::read(Addr address) const
{
    T data;
    readBlob(address, (uint8_t*)&data, sizeof(T));
    return data;
}

template <typename T>
void
PortProxy::write(Addr address, T data) const
{
    writeBlob(address, (uint8_t*)&data, sizeof(T));
}

template <typename T>
T
PortProxy::read(Addr address, ByteOrder byte_order) const
{
    T data;
    readBlob(address, (uint8_t*)&data, sizeof(T));
    return gtoh(data, byte_order);
}

template <typename T>
void
PortProxy::write(Addr address, T data, ByteOrder byte_order) const
{
    data = htog(data, byte_order);
    writeBlob(address, (uint8_t*)&data, sizeof(T));
}

#endif // __MEM_PORT_PROXY_HH__