commit f0e2caf84fbbf225e46cbda61e45fc5727d4d885
author Austin Harris <austinharris@utexas.edu> Mon Feb 04 17:48:52 2019 -0600
committer Austin Harris <austin.dane.harris@gmail.com> Tue Feb 05 00:09:42 2019 +0000
tree 946257111d4f66a90b768e79b24c99b622e8c174
parent 2775f55447edb344d99f30273ad93fea515d7e2b

riscv: Get rid of ISA specific register types in Interrupts.

Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/16122
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/riscv/interrupts.hh

diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 729af6f..912bf45 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -125,10 +125,10 @@
         ip = 0;
     }
 
-    MiscReg readIP() const { return (MiscReg)ip.to_ulong(); }
-    MiscReg readIE() const { return (MiscReg)ie.to_ulong(); }
-    void setIP(const MiscReg& val) { ip = val; }
-    void setIE(const MiscReg& val) { ie = val; }
+    uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
+    uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
+    void setIP(const uint64_t& val) { ip = val; }
+    void setIE(const uint64_t& val) { ie = val; }
 
     void
     serialize(CheckpointOut &cp)
@@ -150,4 +150,4 @@
 
 } // namespace RiscvISA
 
-#endif // __ARCH_RISCV_INTERRUPT_HH__
\ No newline at end of file
+#endif // __ARCH_RISCV_INTERRUPT_HH__