src/arch/arm/insts/tme64.hh

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#ifndef __ARCH_ARM_INSTS_TME64_HH__
#define __ARCH_ARM_INSTS_TME64_HH__

#include "arch/arm/insts/macromem.hh"
#include "arch/arm/insts/pred_inst.hh"
#include "arch/arm/insts/static_inst.hh"

namespace gem5
{

namespace ArmISAInst {

class MicroTmeOp : public ArmISA::MicroOp
{
  protected:
    MicroTmeOp(const char *mnem, ArmISA::ExtMachInst machInst,
               OpClass __opClass)
      : ArmISA::MicroOp(mnem, machInst, __opClass)
    {}
};

class MicroTmeBasic64 : public MicroTmeOp
{
  protected:
    MicroTmeBasic64(const char *mnem, ArmISA::ExtMachInst machInst,
                    OpClass __opClass) :
                    MicroTmeOp(mnem, machInst, __opClass)
    {}

    std::string generateDisassembly(Addr pc,
                                    const loader::SymbolTable *symtab) const;
};

class TmeImmOp64 : public ArmISA::ArmStaticInst
{
  protected:
    uint64_t imm;

    TmeImmOp64(const char *mnem, ArmISA::ExtMachInst machInst,
               OpClass __opClass, uint64_t _imm)
      : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
        imm(_imm)
    {}

    std::string generateDisassembly(Addr pc,
                                    const loader::SymbolTable *symtab) const;
};

class TmeRegNone64 : public ArmISA::ArmStaticInst
{
  protected:
    RegIndex dest;

    TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
                 OpClass __opClass, RegIndex _dest)
      : ArmISA::ArmStaticInst(mnem, machInst, __opClass),
        dest(_dest)
    {}

    std::string generateDisassembly(Addr pc,
                                    const loader::SymbolTable *symtab) const;
};

class Tstart64 : public TmeRegNone64
{
  private:
    RegId destRegIdxArr[1];

  public:
    Tstart64(ArmISA::ExtMachInst, RegIndex);

    Fault execute(ExecContext *, trace::InstRecord *) const;
    Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
    Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};

class Ttest64 : public TmeRegNone64
{
  private:
    RegId destRegIdxArr[1];

  public:
    Ttest64(ArmISA::ExtMachInst, RegIndex);

    Fault execute(ExecContext *, trace::InstRecord *) const;
};

class Tcancel64 : public TmeImmOp64
{
  public:
    Tcancel64(ArmISA::ExtMachInst, uint64_t);

    Fault execute(ExecContext *, trace::InstRecord *) const;
    Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
    Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};

class MicroTfence64 : public MicroTmeBasic64
{
  public:
    MicroTfence64(ArmISA::ExtMachInst);

    Fault execute(ExecContext *, trace::InstRecord *) const;
    Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
    Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};

class MicroTcommit64 : public MicroTmeBasic64
{
  public:
    MicroTcommit64(ArmISA::ExtMachInst);

    Fault execute(ExecContext *, trace::InstRecord *) const;
    Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
    Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};


class MacroTmeOp : public ArmISA::PredMacroOp
{
  protected:
    MacroTmeOp(const char *mnem, ArmISA::ExtMachInst _machInst,
               OpClass __opClass);
};

class Tcommit64 : public MacroTmeOp
{
  public:
    Tcommit64(ArmISA::ExtMachInst _machInst);
};

} // namespace ArmISAInst
} // namespace gem5

#endif