arch,sim: Promote the m5ops_base param to the System base class.
This mechanism is shared between ARM and x86, even if x86 has a typical
address range it choses to use. By moving this to the base class, it's
now possible for anybody to find out where the m5 ops are, and no ISA
specific assumptions need to be made.
Because the x86 address is well known, it's set in the x86 System
subclass as the default.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187
Change-Id: Ifdb9f5cd1ce38b3c4dafa7566c50f245f14cf790
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23180
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5629ab5..0e64215 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -93,10 +93,6 @@
semihosting = Param.ArmSemihosting(NULL,
"Enable support for the Arm semihosting by settings this parameter")
- m5ops_base = Param.Addr(0,
- "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
- "to disable.")
-
dtb_filename = Param.String("",
"File that contains the Device Tree Blob. Don't use DTB if empty.")
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index c3c2b8d..5c32059 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -75,9 +75,6 @@
_sveVL(p->sve_vl),
_haveLSE(p->have_lse),
_havePAN(p->have_pan),
- _m5opRange(p->m5ops_base ?
- RangeSize(p->m5ops_base, 0x10000) :
- AddrRange(1, 0)), // Create an empty range if disabled
semihosting(p->semihosting),
multiProc(p->multi_proc)
{
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index a904805..90fed14 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -139,12 +139,6 @@
const unsigned _havePAN;
/**
- * Range for memory-mapped m5 pseudo ops. The range will be
- * invalid/empty if disabled.
- */
- const AddrRange _m5opRange;
-
- /**
* True if the Semihosting interface is enabled.
*/
ArmSemihosting *const semihosting;
diff --git a/src/sim/System.py b/src/sim/System.py
index 619b54e..e49d26a 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -125,5 +125,12 @@
# Provide list of domains that need to be controlled by the handler
dvfs_handler = DVFSHandler()
+ # SE mode doesn't use the ISA System subclasses, and so we need to set an
+ # ISA specific value in this class directly.
+ m5ops_base = Param.Addr(
+ 0xffff0000 if buildEnv['TARGET_ISA'] == 'x86' else 0,
+ "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
+ "to disable.")
+
if buildEnv['USE_KVM']:
kvm_vm = Param.KvmVM(NULL, 'KVM VM (i.e., shared memory domain)')
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 97ebd1d..0cc328c 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -111,6 +111,9 @@
numWorkIds(p->num_work_ids),
thermalModel(p->thermal_model),
_params(p),
+ _m5opRange(p->m5ops_base ?
+ RangeSize(p->m5ops_base, 0x10000) :
+ AddrRange(1, 0)), // Create an empty range if disabled
totalNumInsts(0),
redirectPaths(p->redirect_paths)
{
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 338b126..6c63b32 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -567,6 +567,12 @@
protected:
Params *_params;
+ /**
+ * Range for memory-mapped m5 pseudo ops. The range will be
+ * invalid/empty if disabled.
+ */
+ const AddrRange _m5opRange;
+
public:
System(Params *p);
~System();
