| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| eventq_index=0 |
| init_param=0 |
| kernel= |
| kernel_addr_check=true |
| load_addr_mask=1099511627775 |
| load_offset=0 |
| mem_mode=timing |
| mem_ranges= |
| memories=system.physmem |
| mmap_using_noreserve=false |
| num_work_ids=16 |
| readfile= |
| symbolfile= |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[1] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| clock=1000 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.cpu0] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu0.l1c.cpu_side |
| |
| [system.cpu0.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu0.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu0.port |
| mem_side=system.toL2Bus.slave[0] |
| |
| [system.cpu0.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu1] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu1.l1c.cpu_side |
| |
| [system.cpu1.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu1.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu1.port |
| mem_side=system.toL2Bus.slave[1] |
| |
| [system.cpu1.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu2] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu2.l1c.cpu_side |
| |
| [system.cpu2.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu2.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu2.port |
| mem_side=system.toL2Bus.slave[2] |
| |
| [system.cpu2.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu3] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu3.l1c.cpu_side |
| |
| [system.cpu3.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu3.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu3.port |
| mem_side=system.toL2Bus.slave[3] |
| |
| [system.cpu3.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu4] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu4.l1c.cpu_side |
| |
| [system.cpu4.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu4.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu4.port |
| mem_side=system.toL2Bus.slave[4] |
| |
| [system.cpu4.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu5] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu5.l1c.cpu_side |
| |
| [system.cpu5.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu5.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu5.port |
| mem_side=system.toL2Bus.slave[5] |
| |
| [system.cpu5.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu6] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu6.l1c.cpu_side |
| |
| [system.cpu6.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu6.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu6.port |
| mem_side=system.toL2Bus.slave[6] |
| |
| [system.cpu6.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu7] |
| type=MemTest |
| children=l1c |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| interval=1 |
| max_loads=100000 |
| percent_functional=50 |
| percent_reads=65 |
| percent_uncacheable=10 |
| progress_check=5000000 |
| progress_interval=10000 |
| size=65536 |
| suppress_func_warnings=false |
| system=system |
| port=system.cpu7.l1c.cpu_side |
| |
| [system.cpu7.l1c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tags=system.cpu7.l1c.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu7.port |
| mem_side=system.toL2Bus.slave[7] |
| |
| [system.cpu7.l1c.tags] |
| type=LRU |
| assoc=4 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=32768 |
| |
| [system.cpu_clk_domain] |
| type=SrcClockDomain |
| clock=500 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.dvfs_handler] |
| type=DVFSHandler |
| domains= |
| enable=false |
| eventq_index=0 |
| sys_clk_domain=system.clk_domain |
| transition_latency=100000000 |
| |
| [system.l2c] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=8 |
| clk_domain=system.cpu_clk_domain |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=20 |
| is_top_level=false |
| max_miss_count=0 |
| mshrs=20 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=20 |
| sequential_access=false |
| size=65536 |
| system=system |
| tags=system.l2c.tags |
| tgts_per_mshr=12 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.toL2Bus.master[0] |
| mem_side=system.membus.slave[0] |
| |
| [system.l2c.tags] |
| type=LRU |
| assoc=8 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=20 |
| sequential_access=false |
| size=65536 |
| |
| [system.membus] |
| type=CoherentXBar |
| clk_domain=system.clk_domain |
| eventq_index=0 |
| forward_latency=4 |
| frontend_latency=3 |
| response_latency=2 |
| snoop_filter=Null |
| snoop_response_latency=4 |
| system=system |
| use_default_range=false |
| width=16 |
| master=system.physmem.port |
| slave=system.l2c.mem_side system.system_port |
| |
| [system.physmem] |
| type=SimpleMemory |
| bandwidth=73.000000 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| eventq_index=0 |
| in_addr_map=true |
| latency=30000 |
| latency_var=0 |
| null=false |
| range=0:134217727 |
| port=system.membus.master[0] |
| |
| [system.toL2Bus] |
| type=CoherentXBar |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| forward_latency=0 |
| frontend_latency=1 |
| response_latency=1 |
| snoop_filter=Null |
| snoop_response_latency=1 |
| system=system |
| use_default_range=false |
| width=32 |
| master=system.l2c.cpu_side |
| slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side |
| |
| [system.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |
