commit fc63dc6221357a2d1e16b3295610528452ac1402
author Gabe Black <gabeblack@google.com> Wed Aug 28 16:55:33 2019 -0700
committer Gabe Black <gabeblack@google.com> Wed Oct 02 04:28:06 2019 +0000
tree f90fcb0c438fce5ab5cc016d79f393d98a29fb33
parent f89f85d255e2192fa2aab5dd168eb9372c41d09c

fastmodel: Implement a custom sendFunctional for CortexA76x1.

Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc

diff --git a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc b/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc
index b680ce4..1ac0acb 100644
--- a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc
+++ b/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.cc
@@ -33,6 +33,7 @@
 #include "base/logging.hh"
 #include "params/FastModelCortexA76x1.hh"
 #include "sim/core.hh"
+#include "systemc/tlm_bridge/gem5_to_tlm.hh"
 
 namespace FastModel
 {
@@ -60,7 +61,8 @@
       cntpnsirqWrapper(cntpnsirq, params.name + ".cntpnsirq", -1),
       clockChanged(Iris::ClockEventName.c_str()),
       clockPeriod(Iris::PeriodAttributeName.c_str()),
-      gem5Cpu(Iris::Gem5CpuAttributeName.c_str())
+      gem5Cpu(Iris::Gem5CpuAttributeName.c_str()),
+      sendFunctional(Iris::SendFunctionalAttributeName.c_str())
 {
     clockRateControl.bind(clock_rate_s);
 
@@ -201,6 +203,18 @@
     SC_METHOD(clockChangeHandler);
     dont_initialize();
     sensitive << clockChanged;
+
+    sendFunctional.value = [this](PacketPtr pkt) { sendFunc(pkt); };
+    add_attribute(sendFunctional);
+}
+
+void
+CortexA76x1::sendFunc(PacketPtr pkt)
+{
+    auto *trans = sc_gem5::packet2payload(pkt);
+    panic_if(scx_evs_CortexA76x1::amba->transport_dbg(*trans) !=
+            trans->get_data_length(), "Didn't send entire functional packet!");
+    trans->release();
 }
 
 Port &

src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh

diff --git a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh b/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh
index 00f843b..0d20479 100644
--- a/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh
+++ b/src/arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh
@@ -34,6 +34,7 @@
 
 #include "arch/arm/fastmodel/amba_ports.hh"
 #include "arch/arm/fastmodel/protocol/exported_clock_rate_control.hh"
+#include "mem/port_proxy.hh"
 #include "params/FastModelCortexA76x1.hh"
 #include "scx_evs_CortexA76x1.h"
 #include "systemc/ext/core/sc_event.hh"
@@ -79,6 +80,9 @@
     sc_core::sc_event clockChanged;
     sc_core::sc_attribute<Tick> clockPeriod;
     sc_core::sc_attribute<::BaseCPU *> gem5Cpu;
+    sc_core::sc_attribute<PortProxy::SendFunctionalFunc> sendFunctional;
+
+    void sendFunc(PacketPtr pkt);
 
     void clockChangeHandler();