src/dev/arm/SConscript

# -*- mode:python -*-

# Copyright (c) 2009, 2012-2013, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Import('*')

SimObject('AbstractNVM.py', sim_objects=['AbstractNVM'], tags='arm isa')
SimObject('Display.py', sim_objects=['Display'], tags='arm isa')
SimObject('Doorbell.py', sim_objects=['Doorbell'], tags='arm isa')
SimObject('FlashDevice.py', sim_objects=['FlashDevice'],
        enums=['DataDistribution'], tags='arm isa')
SimObject('GenericTimer.py', sim_objects=[
    'SystemCounter', 'GenericTimer', 'GenericTimerFrame',
    'GenericTimerMem'], tags='arm isa')
SimObject('Gic.py', sim_objects=[
    'BaseGic', 'ArmInterruptPin', 'ArmSPI', 'ArmPPI', 'ArmSigInterruptPin',
    'GicV2', 'Gicv2mFrame', 'Gicv2m', 'VGic', 'Gicv3Its', 'Gicv3'],
    enums=['ArmInterruptType'], tags='arm isa')
SimObject('RealView.py', sim_objects=[
    'AmbaPioDevice', 'AmbaIntDevice', 'AmbaDmaDevice', 'A9SCU',
    'GenericArmPciHost', 'RealViewCtrl', 'RealViewOsc',
    'RealViewTemperatureSensor', 'AmbaFake', 'Pl011', 'Sp804', 'Sp805',
    'GenericWatchdog', 'CpuLocalTimer', 'PL031', 'Pl050', 'Pl111', 'HDLcd',
    'FVPBasePwrCtrl', 'RealView'],
    enums=['ArmPciIntRouting'], tags='arm isa')
SimObject('SMMUv3.py', sim_objects=['SMMUv3DeviceInterface', 'SMMUv3'],
    tags='arm isa')
SimObject('UFSHostDevice.py', sim_objects=['UFSHostDevice'], tags='arm isa')
SimObject('EnergyCtrl.py', sim_objects=['EnergyCtrl'], tags='arm isa')
SimObject('NoMali.py', sim_objects=['NoMaliGpu', 'CustomNoMaliGpu'],
    enums=['NoMaliGpuType'], tags='arm isa')
SimObject('VirtIOMMIO.py', sim_objects=['MmioVirtIO'], tags='arm isa')
if env['USE_ARM_FASTMODEL']:
    SimObject('VExpressFastmodel.py', tags='arm isa')

Source('a9scu.cc', tags='arm isa')
Source('amba_device.cc', tags='arm isa')
Source('amba_fake.cc', tags='arm isa')
Source('base_gic.cc', tags='arm isa')
Source('display.cc', tags='arm isa')
Source('flash_device.cc', tags='arm isa')
Source('generic_timer.cc', tags='arm isa')
Source('gic_v2.cc', tags='arm isa')
Source('gic_v2m.cc', tags='arm isa')
Source('gic_v3.cc', tags='arm isa')
Source('gic_v3_cpu_interface.cc', tags='arm isa')
Source('gic_v3_distributor.cc', tags='arm isa')
Source('gic_v3_redistributor.cc', tags='arm isa')
Source('gic_v3_its.cc', tags='arm isa')
Source('pl011.cc', tags='arm isa')
Source('pl111.cc', tags='arm isa')
Source('hdlcd.cc', tags='arm isa')
Source('kmi.cc', tags='arm isa')
Source('smmu_v3.cc', tags='arm isa');
Source('smmu_v3_caches.cc', tags='arm isa');
Source('smmu_v3_cmdexec.cc', tags='arm isa');
Source('smmu_v3_events.cc', tags='arm isa');
Source('smmu_v3_ports.cc', tags='arm isa');
Source('smmu_v3_proc.cc', tags='arm isa');
Source('smmu_v3_deviceifc.cc', tags='arm isa');
Source('smmu_v3_transl.cc', tags='arm isa');
Source('timer_sp804.cc', tags='arm isa')
Source('watchdog_generic.cc', tags='arm isa')
Source('watchdog_sp805.cc', tags='arm isa')
Source('gpu_nomali.cc', tags='arm isa')
Source('pci_host.cc', tags='arm isa')
Source('rv_ctrl.cc', tags='arm isa')
Source('realview.cc', tags='arm isa')
Source('rtc_pl031.cc', tags='arm isa')
Source('timer_cpulocal.cc', tags='arm isa')
Source('vgic.cc', tags='arm isa')
Source('vio_mmio.cc', tags='arm isa')
Source('ufs_device.cc', tags='arm isa')
Source('energy_ctrl.cc', tags='arm isa')
Source('fvp_base_pwr_ctrl.cc', tags='arm isa')

DebugFlag('AMBA', tags='arm isa')
DebugFlag('FlashDevice', tags='arm isa')
DebugFlag('HDLcd', tags='arm isa')
DebugFlag('PL111', tags='arm isa')
DebugFlag('GICV2M', tags='arm isa')
DebugFlag('Pl050', tags='arm isa')
DebugFlag('GIC', tags='arm isa')
DebugFlag('ITS', tags='arm isa')
DebugFlag('RVCTRL', tags='arm isa')
DebugFlag('SMMUv3', tags='arm isa')
DebugFlag('SMMUv3Hazard', tags='arm isa')
DebugFlag('Sp805', tags='arm isa')
DebugFlag('EnergyCtrl', tags='arm isa')
DebugFlag('FVPBasePwrCtrl', tags='arm isa')
DebugFlag('UFSHostDevice', tags='arm isa')
DebugFlag('VGIC', tags='arm isa')
DebugFlag('NoMali', tags='arm isa')