src/cpu/simple/noncaching.cc

/*
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 * this software without specific prior written permission.
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#include "cpu/simple/noncaching.hh"

NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
    : AtomicSimpleCPU(p)
{
}

void
NonCachingSimpleCPU::verifyMemoryMode() const
{
    if (!(system->isAtomicMode() && system->bypassCaches())) {
        fatal("The direct CPU requires the memory system to be in the "
              "'atomic_noncaching' mode.\n");
    }
}

Tick
NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
{
    if (system->isMemAddr(pkt->getAddr())) {
        system->getPhysMem().access(pkt);
        return 0;
    } else {
        return port.sendAtomic(pkt);
    }
}

NonCachingSimpleCPU *
NonCachingSimpleCPUParams::create()
{
    numThreads = 1;
    if (!FullSystem && workload.size() != 1)
        fatal("only one workload allowed");
    return new NonCachingSimpleCPU(this);
}