commit fd95c6848501c01ee1ad1061ae91aebe455913cb
author Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Aug 08 10:29:22 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Aug 12 18:17:45 2019 +0000
tree 729167001b9fa920c7b624f5ebc7d4302a20402c
parent 377860544f28064c583f440e87fbb37567bae428

dev-arm: Enable DTB autogeneration in GICv3

Change-Id: I539ae5ae74bc6f42f291441594a0d14c98e687f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20053
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/Gic.py

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index b431a6e..d2e2ace 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -192,7 +192,7 @@
     cxx_header = "dev/arm/gic_v3.hh"
 
     # Used for DTB autogeneration
-    _state = FdtState(addr_cells=2, interrupt_cells=3)
+    _state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
 
     its = Param.Gicv3Its(Gicv3Its(), "GICv3 Interrupt Translation Service")
 
@@ -214,3 +214,39 @@
         "redistributors")
 
     gicv4 = Param.Bool(True, "GICv4 extension available")
+
+    def interruptCells(self, int_type, int_num, int_flag):
+        """
+        Interupt cells generation helper:
+        Following specifications described in
+
+        Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
+        """
+        prop = self._state.interruptCells(0)
+        assert len(prop) >= 3
+        prop[0] = int_type
+        prop[1] = int_num
+        prop[2] = int_flag
+        return prop
+
+    def generateDeviceTree(self, state):
+        node = FdtNode("interrupt-controller")
+        node.appendCompatible(["arm,gic-v3"])
+        node.append(self._state.interruptCellsProperty())
+        node.append(self._state.addrCellsProperty())
+        node.append(self._state.sizeCellsProperty())
+        node.append(FdtProperty("interrupt-controller"))
+
+        regs = (
+            state.addrCells(self.dist_addr) +
+            state.sizeCells(0x10000) +
+            state.addrCells(self.redist_addr) +
+            state.sizeCells(0x2000000) )
+
+        node.append(FdtPropertyWords("reg", regs))
+        node.append(FdtPropertyWords("interrupts",
+            self.interruptCells(1, int(self.maint_int.num)-16, 0xf04)))
+
+        node.appendPhandle(self)
+
+        yield node