| // |
| // Copyright (c) 2010 ARM Limited |
| // All rights reserved |
| // |
| // The license below extends only to copyright in the software and shall |
| // not be construed as granting a license to any other intellectual |
| // property including but not limited to intellectual property relating |
| // to a hardware implementation of the functionality of the software |
| // licensed hereunder. You may use the software subject to the license |
| // terms below provided that you ensure that this notice is replicated |
| // unmodified and in its entirety in all distributions of the software, |
| // modified or unmodified, in source code or in binary form. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| /// |
| |
| def format M5ops() {{ |
| decode_block = ''' |
| { |
| const uint32_t m5func = bits(machInst, 23, 16); |
| switch(m5func) { |
| case M5OP_ARM: return new Arm(machInst); |
| case M5OP_QUIESCE: return new Quiesce(machInst); |
| case M5OP_QUIESCE_NS: return new QuiesceNs(machInst); |
| case M5OP_QUIESCE_CYCLE: return new QuiesceCycles(machInst); |
| case M5OP_QUIESCE_TIME: return new QuiesceTime(machInst); |
| case M5OP_RPNS: return new Rpns(machInst); |
| case M5OP_WAKE_CPU: return new WakeCPU(machInst); |
| case M5OP_DEPRECATED1: return new Deprecated_ivlb(machInst); |
| case M5OP_DEPRECATED2: return new Deprecated_ivle(machInst); |
| case M5OP_DEPRECATED3: return new Deprecated_exit (machInst); |
| case M5OP_EXIT: return new M5exit(machInst); |
| case M5OP_FAIL: return new M5fail(machInst); |
| case M5OP_SUM: return new M5sum(machInst); |
| case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst); |
| case M5OP_INIT_PARAM: return new Initparam(machInst); |
| case M5OP_RESET_STATS: return new Resetstats(machInst); |
| case M5OP_DUMP_STATS: return new Dumpstats(machInst); |
| case M5OP_DUMP_RESET_STATS: return new Dumpresetstats(machInst); |
| case M5OP_CHECKPOINT: return new M5checkpoint(machInst); |
| case M5OP_WRITE_FILE: return new M5writefile(machInst); |
| case M5OP_READ_FILE: return new M5readfile(machInst); |
| case M5OP_DEBUG_BREAK: return new M5break(machInst); |
| case M5OP_SWITCH_CPU: return new M5switchcpu(machInst); |
| case M5OP_ADD_SYMBOL: return new M5addsymbol(machInst); |
| case M5OP_PANIC: return new M5panic(machInst); |
| case M5OP_WORK_BEGIN: return new M5workbegin(machInst); |
| case M5OP_WORK_END: return new M5workend(machInst); |
| default: return new Unknown(machInst); |
| } |
| } |
| ''' |
| }}; |
