src/dev/riscv/hifive.cc

/*
 * Copyright (c) 2021 Huawei International
 * Copyright (c) 2023 Google LLC
 * All rights reserved
 *
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 * not be construed as granting a license to any other intellectual
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#include "dev/riscv/hifive.hh"

#include "dev/riscv/clint.hh"
#include "dev/riscv/plic.hh"
#include "params/HiFiveBase.hh"
#include "sim/system.hh"

namespace gem5
{

using namespace RiscvISA;

HiFiveBase::HiFiveBase(const Params &params) :
    Platform(params),
    clint(params.clint), plic(params.plic),
    uartIntID(params.uart_int_id)
{
    fatal_if(clint == nullptr, "CLINT should not be NULL");
    fatal_if(plic == nullptr, "PLIC should not be NULL");
}

void
HiFiveBase::postConsoleInt()
{
    plic->post(uartIntID);
}

void
HiFiveBase::clearConsoleInt()
{
    plic->clear(uartIntID);
}

void
HiFiveBase::postPciInt(int line)
{
    plic->post(line);
}

void
HiFiveBase::clearPciInt(int line)
{
    plic->clear(line);
}

void
HiFiveBase::serialize(CheckpointOut &cp) const
{
}

void
HiFiveBase::unserialize(CheckpointIn &cp)
{
}

} // namespace gem5