| # -*- mode:python -*- | |
| # Copyright (c) 2006 The Regents of The University of Michigan | |
| # All rights reserved. | |
| # | |
| # Redistribution and use in source and binary forms, with or without | |
| # modification, are permitted provided that the following conditions are | |
| # met: redistributions of source code must retain the above copyright | |
| # notice, this list of conditions and the following disclaimer; | |
| # redistributions in binary form must reproduce the above copyright | |
| # notice, this list of conditions and the following disclaimer in the | |
| # documentation and/or other materials provided with the distribution; | |
| # neither the name of the copyright holders nor the names of its | |
| # contributors may be used to endorse or promote products derived from | |
| # this software without specific prior written permission. | |
| # | |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| Import('*') | |
| SimObject('ClockedObject.py', sim_objects=['ClockedObject']) | |
| SimObject('TickedObject.py', sim_objects=['TickedObject']) | |
| SimObject('Workload.py', sim_objects=[ | |
| 'Workload', 'StubWorkload', 'KernelWorkload', 'SEWorkload']) | |
| SimObject('Root.py', sim_objects=['Root']) | |
| SimObject('ClockDomain.py', sim_objects=[ | |
| 'ClockDomain', 'SrcClockDomain', 'DerivedClockDomain']) | |
| SimObject('VoltageDomain.py', sim_objects=['VoltageDomain']) | |
| SimObject('System.py', sim_objects=['System'], enums=['MemoryMode']) | |
| SimObject('DVFSHandler.py', sim_objects=['DVFSHandler']) | |
| SimObject('SubSystem.py', sim_objects=['SubSystem']) | |
| SimObject('RedirectPath.py', sim_objects=['RedirectPath']) | |
| SimObject('PowerState.py', sim_objects=['PowerState'], enums=['PwrState']) | |
| SimObject('PowerDomain.py', sim_objects=['PowerDomain']) | |
| SimObject('SignalPort.py', sim_objects=[]) | |
| Source('async.cc') | |
| Source('backtrace_%s.cc' % env['BACKTRACE_IMPL'], add_tags='gem5 trace') | |
| Source('bufval.cc') | |
| Source('core.cc') | |
| Source('cur_tick.cc', add_tags='gem5 trace') | |
| Source('tags.cc') | |
| Source('cxx_config.cc') | |
| Source('cxx_manager.cc') | |
| Source('cxx_config_ini.cc') | |
| Source('debug.cc') | |
| Source('drain.cc', add_tags='gem5 drain') | |
| Source('py_interact.cc', add_tags='python') | |
| Source('eventq.cc', add_tags='gem5 events') | |
| Source('futex_map.cc') | |
| Source('global_event.cc', add_tags='gem5 drain') | |
| Source('globals.cc') | |
| Source('init.cc', add_tags='python') | |
| Source('init_signals.cc') | |
| Source('main.cc', tags='main') | |
| Source('kernel_workload.cc') | |
| Source('port.cc') | |
| Source('python.cc', add_tags='python') | |
| Source('redirect_path.cc') | |
| Source('root.cc') | |
| Source('serialize.cc', add_tags='gem5 serialize') | |
| Source('se_workload.cc') | |
| Source('sim_events.cc', add_tags='gem5 drain') | |
| Source('sim_object.cc') | |
| Source('sub_system.cc') | |
| Source('ticked_object.cc') | |
| Source('simulate.cc') | |
| Source('stat_control.cc') | |
| Source('stat_register.cc', add_tags='python') | |
| Source('clock_domain.cc') | |
| Source('voltage_domain.cc') | |
| Source('se_signal.cc') | |
| Source('linear_solver.cc') | |
| Source('system.cc') | |
| Source('dvfs_handler.cc') | |
| Source('clocked_object.cc') | |
| Source('mathexpr.cc') | |
| Source('power_state.cc') | |
| Source('power_domain.cc') | |
| Source('stats.cc') | |
| Source('workload.cc') | |
| Source('mem_pool.cc') | |
| env.TagImplies('gem5 drain', ['gem5 events', 'gem5 trace']) | |
| env.TagImplies('gem5 events', ['gem5 serialize', 'gem5 trace']) | |
| env.TagImplies('gem5 serialize', 'gem5 trace') | |
| GTest('bufval.test', 'bufval.test.cc', 'bufval.cc') | |
| GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc') | |
| GTest('globals.test', 'globals.test.cc', 'globals.cc', | |
| with_tag('gem5 serialize')) | |
| GTest('guest_abi.test', 'guest_abi.test.cc') | |
| GTest('port.test', 'port.test.cc', 'port.cc') | |
| GTest('proxy_ptr.test', 'proxy_ptr.test.cc') | |
| GTest('serialize.test', 'serialize.test.cc', with_tag('gem5 serialize')) | |
| GTest('serialize_handlers.test', 'serialize_handlers.test.cc') | |
| SimObject('InstTracer.py', sim_objects=['InstTracer']) | |
| SimObject('Process.py', sim_objects=['Process', 'EmulatedDriver']) | |
| Source('faults.cc') | |
| Source('process.cc') | |
| Source('fd_array.cc') | |
| Source('fd_entry.cc') | |
| Source('mem_state.cc') | |
| Source('pseudo_inst.cc') | |
| Source('syscall_emul.cc') | |
| Source('syscall_desc.cc') | |
| Source('vma.cc') | |
| DebugFlag('Checkpoint') | |
| DebugFlag('Config') | |
| DebugFlag('CxxConfig') | |
| DebugFlag('Drain') | |
| DebugFlag('Event') | |
| DebugFlag('Flow') | |
| DebugFlag('IPI') | |
| DebugFlag('IPR') | |
| DebugFlag('Interrupt') | |
| DebugFlag('Loader') | |
| DebugFlag('PseudoInst') | |
| DebugFlag('Stack') | |
| DebugFlag('SyscallBase') | |
| DebugFlag('SyscallVerbose') | |
| DebugFlag('TimeSync') | |
| DebugFlag('Thread') | |
| DebugFlag('Timer') | |
| DebugFlag('VtoPhys') | |
| DebugFlag('WorkItems') | |
| DebugFlag('ClockDomain') | |
| DebugFlag('VoltageDomain') | |
| DebugFlag('DVFS') | |
| DebugFlag('Vma') | |
| DebugFlag('PowerDomain') | |
| CompoundFlag('SyscallAll', [ 'SyscallBase', 'SyscallVerbose']) |