| # Copyright (c) 2022 Jarvis Jia, Jing Qu, Matt Sinclair, & Mingyuan Xiang |
| # All Rights Reserved. |
| # |
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| |
| # This test is targeting stores |
| # Access pattern: A, C, E, G, A, C, E, G, I, A |
| # Each letter represents a 64-bit address range. |
| |
| # The [] indicate two different sets, and each set has four ways. |
| # [set0way0, set0way1, set0way2, set0way3], |
| # [set1way0, set1way1, set1way2, set1way3], |
| # If you have a 512B cache with 4-way associativity, and each cache |
| # line is 64B with LRU replacement policy, you will observe: |
| # m, m, m, m, h, h, h, h, m, m, where 'h' means |
| # hit and 'm' means miss. |
| |
| # Explanation of this result: |
| # A, C, E, G are misses, now the cache stores ([A*, C, E, G],[ , , ,]). |
| # A is marked as the LRU address range. |
| # A, C, E, G then hits, and the cache stores ([A*, C, E, G],[ , , ,]). |
| # I searches for a victim and selects A. Now the cache stores ([E, C*, I, G],[ , , ,]). |
| # A searches for a victim and selects C. Now the cache stores ([E, A, I*, G],[ , , ,]). |
| |
| from m5.objects.ReplacementPolicies import LRURP as rp |
| |
| |
| def python_generator(generator): |
| yield generator.createLinear(60000, 0, 63, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 128, 191, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 256, 319, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 384, 447, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 0, 63, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 128, 191, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 256, 319, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 384, 447, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 512, 575, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(60000, 0, 63, 64, 30000, 30000, 0, 0) |
| yield generator.createLinear(30000, 0, 0, 0, 30000, 30000, 0, 0) |
| |
| yield generator.createExit(0) |